Patents by Inventor Shlomi Uziel

Shlomi Uziel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240038392
    Abstract: A system and method for identifying differential diagnoses using a multi-classifier disease model. The method includes constructing the multi-classifier disease model based on at least one disease profile, wherein the multi-classifier disease model is a machine learning network of at least one disease and a plurality of health variables; extracting at least one patient health variable from input patient data, wherein the input patient data indicates a patient condition; applying the multi-classifier disease model to the at least one patient health variable to determine probabilities for the at least one disease; identifying, based on the probabilities of the at least one disease, the differential diagnoses for the input patient data; and providing the differential diagnoses.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 1, 2024
    Applicant: Quai.MD, Ltd.
    Inventors: Golan YONA, Chen SHAPIRA, Shlomi UZIEL
  • Publication number: 20230307133
    Abstract: A system and method for generating a patient-specific clinical meta-pathway. The method includes constructing a clinical meta-pathway graph of a network of pathway states, wherein each pathway state is associated with at least one of a plurality of differential diagnoses of a chief complaint; and wherein each pathway state includes a set of rules that define a connecting pathway state; applying a trained model to the constructed clinical meta-pathway graph to update the set of rules that define the connecting pathway state, wherein the model is trained based on at least historical patient data; navigating through the clinical meta-pathway based on input patient data, wherein the navigation through pathway states is guided by a function of the set of rules; and causing a display of at least a portion of the navigating pathway states.
    Type: Application
    Filed: March 24, 2023
    Publication date: September 28, 2023
    Applicant: Quai.MD, Ltd.
    Inventors: Chen SHAPIRA, Golan YONA, Shlomi UZIEL
  • Patent number: 10607039
    Abstract: A method including receiving a first configuration of a device validated against a design constraint, is provided. A configuration includes stimuli controls and stimuli parameters used as inputs in a device model. The method includes determining a quality of the first configuration based on an estimation of an output parameter including a desired behavior of the device, simulating the device in the first configuration when the first configuration quality overcomes a threshold, and requesting a second configuration of the device when the quality of the first configuration is below the selected threshold. The method also includes obtaining a regression based on multiple, high quality configurations to determine, for the device, a distribution of output parameter values and comparing the distribution of output parameter values with a baseline of a random regression to adjust the machine learning engine according to a target range of output parameter values.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: March 31, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Yael Kinderman, Shlomi Uziel, Ido Avraham, Michele Petracca, Yosinori Watanabe
  • Patent number: 10423741
    Abstract: A method including selecting multiple input parameters of a device configuration environment to perform multiple simulations on an electronic device defined by the device configuration environment is provided. The method with multiple values for the multiple input parameters and a value of an output parameter resulting from the multiple simulations, and extracting a distribution of output parameter values and a distribution of input parameter values from a database. The method also includes finding a correlation involving the multiple input parameters and the output parameter based on a target range of the output parameter, and identifying an expected value of the output parameter using a range of values of the multiple input parameters in the correlation involving the multiple input parameters and the output parameter. A system and a nontransitory, computer-readable medium including instructions to perform the above method are also provided.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: September 24, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Michele Petracca, Yosinori Watanabe, Yael Kinderman, Shlomi Uziel, Ido Avraham
  • Patent number: 8296697
    Abstract: Method and apparatus for performing static analysis optimization in a design verification system is described. In one example, a description of a verification environment having constrained objects is obtained. The constrained objects are analyzed incrementally to create a data structure of nodes. Each node includes a description of variables transitively connected by constraints. At least one of the nodes reuses a description from at least one other node. The data structure is then used during logic design verification.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: October 23, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amit Gal, Shlomi Uziel, Amos Noy
  • Patent number: 7870523
    Abstract: The present invention provides a system and method for resolving a test generation problem involving constraint resolution problems where a verification environment includes constraints that are suitable for resolution using one type of solver for a first domain and other constraints that are suitable for resolution using a different solver in a second domain. The invention further comprises variables and, in instances where at least one variable is in each of the first and second domains, using these solvers to restrict the set of permissible values of variables to be consistent in multiple domains, preferably in all relevant domains. A constraint resolution problem is divided into clusters of constraints connected within a domain, and connected clusters of clusters that are connected through shared variables that are subject to constraints in more than one cluster.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: January 11, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Shlomi Uziel, Amos Noy, Vitaly Lagoon, Yael Kinderman, Amit Gal
  • Publication number: 20080235640
    Abstract: Method and apparatus for performing static analysis optimization in a design verification system is described. In one example, a description of a verification environment having constrained objects is obtained. The constrained objects are analyzed incrementally to create a data structure of nodes. Each node includes a description of variables transitively connected by constraints. At least one of the nodes reuses a description from at least one other node. The data structure is then used during logic design verification.
    Type: Application
    Filed: March 19, 2007
    Publication date: September 25, 2008
    Applicant: Cadence Design Systems, Inc.
    Inventors: Amit Gal, Shlomi Uziel, Amos Noy