Abstract: In one example, an apparatus for integrating sensing and display system includes a first semiconductor layer that includes an image sensor; a second semiconductor layer that includes a display; a third semiconductor layer that includes compute circuits configured to support an image sensing operation by the image sensor and a display operation by the display; and a semiconductor package that encloses the first, second, and third semiconductor layers, the semiconductor package further including a first opening to expose the image sensor and a second opening to expose the display. The first, second, and third semiconductor layers form a first stack structure along a first axis. The third semiconductor layer is sandwiched between the first semiconductor layer and the second semiconductor layer in the first stack structure.

Abstract: Systems and readout methods for foveated sensing may include a pixel array, readout circuitry, and processing logic. The pixel array may have a number of pixels. The readout circuitry may be configured to read image data from the pixel array for each of the plurality of pixels. The processing logic may be configured to identify a number of regions of interest (ROIs) within the pixel array. The processing logic may be configured to associate the image data for the pixels with one or more ROIs. The processing logic may be configured to arrange the image data into data frames. The data frames may include the image data ordered by ROI. Image data for inactive pixels may be removed from the image data and data frames prior to transmission. The processing logic may be configured to transmit the data frames in an order that is based on the ROIs.

Abstract: In some examples, an apparatus comprises an array of pixel cells, and processing circuits associated with blocks of pixel cells of the array of pixel cells and associated with first hierarchical power domains. The apparatus further includes banks of memory devices, each bank of memory devices being associated with a block of pixel cells, to store the quantization results of the associated block of pixel cells, the banks of memory devices further being associated with second hierarchical power domains. The apparatus further includes a processing circuits power state control circuit configured to control a power state of the processing circuits based on programming data targeted at each block of pixel cells and global processing circuits power state control signals, and a memory power state control circuit configured to control a power state of the banks of memory devices based on the programming data and global memory power state control signals.

Abstract: One example apparatus for image sub-sampling with a color grid array includes a super-pixel comprising an array of pixels, each pixel comprising a photodiode configured to generate a charge in response to incoming light, a filter positioned to filter the incoming light, a charge storage device to convert the charge to a voltage, a row-select switch, and a column-select switch; an analog-to-digital converter (“ADC”) connected to each of the charge storage devices of the super-pixel via the respective row-select and column-select switches and configured to selectively convert each respective stored voltage into a pixel value in response to a control signal; and wherein each row-select and column-select switch for a pixel is configured to selectively allow the charge or the voltage to propagate to the respective ADC, the row-select and column-select switches arranged in series.

Abstract: In one embodiment, a computing system accesses a set of 3D locations associated with features in an environment previously captured by a camera from a previous camera pose. The computing system determines a predicted camera pose using the previous camera pose and motion measurements generated using a motion sensor associated with the camera. The computing system projects the set of 3D locations toward the predicted camera pose and onto a 2D image plane associated with the camera. The computing system generates, based on the projected set of 3D locations on the 2D image plane, an activation map specifying a subset of the pixel sensors of the camera that are to be activated. The computing system instructs, using the activation map, the camera to activate the subset of pixel sensors to capture a new image of the environment. The computing system reads pixel values of the new image.

Abstract: In some examples, an apparatus comprises an array of pixel cells, and processing circuits associated with blocks of pixel cells of the array of pixel cells and associated with first hierarchical power domains. The apparatus further includes banks of memory devices, each bank of memory devices being associated with a block of pixel cells, to store the quantization results of the associated block of pixel cells, the banks of memory devices further being associated with second hierarchical power domains. The apparatus further includes a processing circuits power state control circuit configured to control a power state of the processing circuits based on programming data targeted at each block of pixel cells and global processing circuits power state control signals, and a memory power state control circuit configured to control a power state of the banks of memory devices based on the programming data and global memory power state control signals.

Abstract: A method is provided that includes providing a hard-wired integer multiplier circuit configured to multiply a first physical operand and a second physical operand, mapping a first logical operand to a first portion of the first physical operand, mapping a second logical operand to a second portion of the first physical operand, and mapping a third logical operand to the second physical operand. The method further includes multiplying the first physical operand and the second physical operand using the hard-wired integer multiplier circuit to provide a multiplication result that includes a first portion including a product of the first logical operand and the third logical operand, and a second portion including a product of the second logical operand and the third logical operand.

Abstract: A method is provided that includes providing a hard-wired integer multiplier circuit configured to multiply a first physical operand and a second physical operand, mapping a first logical operand to a first portion of the first physical operand, mapping a second logical operand to a second portion of the first physical operand, and mapping a third logical operand to the second physical operand. The method further includes multiplying the first physical operand and the second physical operand using the hard-wired integer multiplier circuit to provide a multiplication result that includes a first portion including a product of the first logical operand and the third logical operand, and a second portion including a product of the second logical operand and the third logical operand.