Abstract: An enhanced digital signal processor (EDSP) includes execution section that includes the following constituents: a processor, an arithmetic logic unit (ALU), a memory device for holding set of instructions for execution selected from enhanced set of instructions, a memory device for holding data, another clock generator for generating a plurality of clock signals coupled to above constituents. Internal communication bus coupled to the above constituents for affording controlled communication between them, a correlator, coupled to the bus, for communication with the execution section. The correlator having an input port for receiving external input data and an output port for outputting data.