Abstract: A method of improving via/contact coverage in an integrated circuit. A standard layout of an interconnect layer comprising plurality of interconnect lines is initially generated with well-known techniques. After generation of the initial layout, the amount of overlap of at least one via by an interconnect line is optimized by increasing the amount of overlap of each side of the via by the interconnect line wherever possible without violating a minimum line separation requirement.

Abstract: A design and method for fabricating devices with reduced loading effect is described. The disclosed design creates dummy features to increase the percentage of material remaining after etch of an active layer. This improves device reliability by preventing resist punch through during etch. Also, yields are improved as no devices are sacrificed to increase the percentage material remaining. Since dummy features are placed on all devices fabricated in a single production process, the percentage material remaining after etch is the same for all devices for a given layer. This allows the same recipe to be used for all devices fabricated by the process, thereby increasing throughput.