Patents by Inventor Shmuel Sagiv

Shmuel Sagiv has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8862439
    Abstract: In one embodiment of the invention, a design verifier is disclosed including a model extractor and a bounded model checker having an arithmetic satisfiability solver. The arithmetic satisfiability solver searches for a solution in the form of a numeric assignment of numbers to variables that satisfies each and every one of the one or more numeric formulas. Conflict in the search, results in the deduction of one or more new numeric formulas that serve to guide the search toward a solution. If the search finds a numeric assignment that satisfies each and every one of the one or more numeric formulas, it indicates that a functional property of the system is violated.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: October 14, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Andreas Kuehlmann, Kenneth L. McMillan, Shmuel Sagiv
  • Patent number: 8656330
    Abstract: In one embodiment of the invention, a design verifier is disclosed including a model extractor and a bounded model checker having an arithmetic satisfiability solver. The arithmetic satisfiability solver searches for a solution in the form of a numeric assignment of numbers to variables that satisfies each and every one of the one or more numeric formulas. Conflict in the search, results in the deduction of one or more new numeric formulas that serve to guide the search toward a solution. If the search finds a numeric assignment that satisfies each and every one of the one or more numeric formulas, it indicates that a functional property of the system is violated.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: February 18, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Andreas Kuehlmann, Kenneth L. McMillan, Shmuel Sagiv
  • Patent number: 6301699
    Abstract: Method for detecting buffer overflow weakness exploitation, including the steps of determining a plurality of threshold parameters, each respective to a buffer overflow weakness exploitation event, analyzing a code to be executed, thereby producing a plurality of validation values, comparing said validation values to the respective ones of the threshold parameters, and determining a buffer overflow weakness exploitation attempt, when at least one of the validation values exceeds the respective one of the threshold parameters.
    Type: Grant
    Filed: March 18, 1999
    Date of Patent: October 9, 2001
    Assignee: Corekt Security Systems, Inc.
    Inventors: Yona Hollander, Ophir Rahman, Shmuel Sagiv, Ury Segal
  • Patent number: 5555412
    Abstract: An aliasing method and apparatus carried out on a digital computer are provided for generating an object code from a source program. An aliasing data structure is defined and includes an initial empty check-list for each variable in the source program. A pseudo variable is constructed to represent each predefined large alias class. The pseudo variable is attached to the check-list of each variable included in the predefined alias class. Inverse alias checking upon use of a variable is provided using the check-lists for the variable.
    Type: Grant
    Filed: November 16, 1995
    Date of Patent: September 10, 1996
    Assignee: International Business Machines Corporation
    Inventors: Keith V. Besaw, Robert J. Donovan, Shmuel Sagiv