Abstract: A multi-tiered filesystem integrates multiple types of storage devices into a contiguous filesystem storage space having regions associated with two or more tiers of storage.

Abstract: A multi-tiered filesystem integrates multiple types of storage devices into a contiguous filesystem storage space having regions associated with two or more tiers of storage.

Abstract: A NAS server runs a native filesystem application that manages the filesystem and also includes a virtualization component that allows third-party data processing applications to run on the NAS server substantially as though running on a separate server while allowing the applications to access filesystem information without use of the network and without the overhead of network protocols and related operating system processing. The virtualization component intercepts certain filesystem-related system calls made by the application and directs processing of those filesystem-related system calls (e.g., by the virtualization component or by the native filesystem application), bypassing certain operating system processes including those relating to network protocol processing.

Abstract: A computer system includes an Intel 80486 microprocessor having an internal cache memory and a local memory tightly coupled to the microprocessor that can respond to memory accesses without requiring the microprocessor to execute a wait state. An external cache memory system is provided to provide additional cache storage to provide copy back capabilities so that data written to the external cache does not have to be automatically written to slower bulk memory. The computer system includes a conventional Industry Standard Architecture bus (ISA-bus) which may include memory on the bus. The computer system may also include an external math coprocessor. In order to preclude storing data from the math coprocessor and from the ISA-bus memory, the external cache memory system includes a cache determination circuit that selectively generates a cache enable signal to the microprocessor and to the external cache memory system so that only cacheable data is stored in the two caches.

Abstract: A memory system for use with a copy back cache system includes a control circuit that reduces the amount of time to complete a copy back/line fill operation in which a first line of data from the cache is stored in the memory system and then a second line of data is retrieved from the memory system and transferred to the cache system. Unlike conventional memory systems where the line of data to be copied back is likely to be stored in the memory system at a row address that differs from the row address of the line of data to be retrieved from the memory system for the line fill, the memory system of the present invention assures that the copy back data and the line fill data are located at the same row address in the memory system. Thus, a single row address can be applied once at the beginning of the copy back/line fill operation, thereby saving the row address precharge time and the row address access time required to switch row addresses between the two portions of the operation.