Abstract: Parallel ML processing of an analog signal in a RLL-coded channel in which (1) vectors for a current state of the channel and the next state of the channel are computed using Walsh transform vector coefficients of the analog signal; (2) current state vectors and next state vectors and values of vectors precomputed in analog matched filters are used to generate vector scalar products which are compared against preselected threshold values for generating binary decision outputs that are used in digital sequential finite state machines to generate ML symbol decisions; and (3) ML symbol decisions are fed back and used to subtract the intersymbol interference value of the current state vector from the vector of the next state to transform the next state vector into an updated current state vector.

Abstract: An apparatus and method for detecting analog signals representing patterns of n-bit RLL-encoded data read from a data storage device. R integrators each integrate the analog signal over successive time periods consisting of a preselected number n of bit cycles, where n>1, weighted by a preselected set of n orthogonal signals that are staircase functions which vary each bit cycle to provide R integrated weighted outputs. The R integrated weighted outputs are converted by a lookup table or read-only memory into an n-bit digital representation corresponding to a unique one of the n-bit analog data patterns.

Abstract: Apparatus and method for implementing a parallelized algorithm for solving the key equation for the decoding of a linear algebraic code. Circuitry implements two computation sequences. One of these executes three multiplication operations and the other executes five multiplication operations, 2t iterations of these two sequences being required to decode t symbols in error. These sequences are coupled such that during each successive 2t iterations, four multiplication operations are executed simultaneously in pairs, the fifth multiplication operation in the other sequence being paired with a multiplication operation in the next iteration of the one sequence. During one of the paired multiplication operations an inverse table look up operation is executed, and during another of the multiplication operations an addition operation is executed. Two consecutive executions of the other sequence are prevented.

Abstract: A computer system architecture and method for performing the Discrete Fourier Transform on a set of N sampled input signals wherein N is chosen to be the product of a group of predetermined relatively prime factors (n.sub.1 .multidot.n.sub.2 .multidot.....multidot.n.sub.L). The present architecture then proceeds to the solution of the Fourier transform via a unique nested loop solution method, wherein each loop is specifically related to each factor and wherein no multiplications are performed in the outer loops said method being further characterized by the fact that the system control is automatically passed to the next inner loop whenever a multiplication instruction is encountered. A unique predetermined sequence of operations which is unique to each factor (n.sub.l) is built into the system controls and automatic control means proceed from one sequence to another depending upon the factors (n) associated with a chosen N.