Patents by Inventor Sho KAMEZAWA
Sho KAMEZAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10901453Abstract: A semiconductor integrated circuit on a rectangular semiconductor substrate includes timing generation circuits having the same functions of generating control clock signals to corresponding input buffer circuits based on a control reference clock signal, and a parallel processing circuit unit divided into circuit blocks having equal areas and corresponding to the timing generation circuits. Each circuit block includes clock distribution networks corresponding to the control clock signals. The parallel processing circuit unit carries out processes in parallel for each clock distribution network. Each clock distribution network includes the input buffer circuit; a clock buffer circuit connected to the input buffer circuit and placed approximately in a central position of the corresponding circuit block relative to the semiconductor substrate longitudinal direction; and end devices. The clock buffer circuit outputs a control output clock signal to be distributed and supplied to the end devices.Type: GrantFiled: February 1, 2019Date of Patent: January 26, 2021Assignee: RICOH COMPANY, LTD.Inventors: Sho Kamezawa, Tohru Kanno
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Patent number: 10824182Abstract: A semiconductor integrated circuit includes a first power supply line, a second power supply line, and a voltage supplied circuit. The first power supply line is connected to a voltage supply source. The second power supply line is connected to the first power supply line at a connection point connecting a first point of the first power supply line and a second point of the second power supply line. The second point is included in a portion of the second power supply line excluding end portions of the second power supply line. The voltage supplied circuit is connected to the second power supply line.Type: GrantFiled: May 1, 2019Date of Patent: November 3, 2020Assignee: Ricoh Company, Ltd.Inventors: Sho Kamezawa, Tohru Kanno
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Publication number: 20200004287Abstract: A semiconductor integrated circuit includes a first power supply line, a second power supply line, and a voltage supplied circuit. The first power supply line is connected to a voltage supply source. The second power supply line is connected to the first power supply line at a connection point connecting a first point of the first power supply line and a second point of the second power supply line. The second point is included in a portion of the second power supply line excluding end portions of the second power supply line. The voltage supplied circuit is connected to the second power supply line.Type: ApplicationFiled: May 1, 2019Publication date: January 2, 2020Inventors: Sho Kamezawa, Tohru Kanno
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Patent number: 10523164Abstract: A semiconductor integrated circuit including a differential amplifier circuit, a first output circuit, a second output circuit, a selection circuit, and a feedback circuit. The differential amplifier circuit is configured to operate at a first source voltage. The first output circuit is configured to receive an output of the differential amplifier circuit, output a first output, and operate at the first source voltage. The second output circuit is configured to receive an output of the differential amplifier circuit, output a second output, and operate at a second source voltage lower than the first source voltage. The selection circuit is configured to select one of the first output from the first output circuit and the second output from the second output circuit according to an operating phase determined by an external control signal. The feedback circuit is connected between the differential amplifier circuit and the selection circuit.Type: GrantFiled: June 27, 2018Date of Patent: December 31, 2019Assignee: RICOH COMPANY, LTD.Inventors: Sho Kamezawa, Tohru Kanno
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Publication number: 20190163231Abstract: A semiconductor integrated circuit on a rectangular semiconductor substrate includes timing generation circuits having the same functions of generating control clock signals to corresponding input buffer circuits based on a control reference clock signal, and a parallel processing circuit unit divided into circuit blocks having equal areas and corresponding to the timing generation circuits. Each circuit block includes clock distribution networks corresponding to the control clock signals. The parallel processing circuit unit carries out processes in parallel for each clock distribution network. Each clock distribution network includes the input buffer circuit; a clock buffer circuit connected to the input buffer circuit and placed approximately in a central position of the corresponding circuit block relative to the semiconductor substrate longitudinal direction; and end devices. The clock buffer circuit outputs a control output clock signal to be distributed and supplied to the end devices.Type: ApplicationFiled: February 1, 2019Publication date: May 30, 2019Applicant: RICOH COMPANY, LTD.Inventors: Sho KAMEZAWA, Tohru KANNO
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Patent number: 10234891Abstract: A semiconductor integrated circuit on a rectangular semiconductor substrate includes timing generation circuits having the same functions of generating control clock signals to corresponding input buffer circuits based on a control reference clock signal, and a parallel processing circuit unit divided into circuit blocks having equal areas and corresponding to the timing generation circuits. Each circuit block includes clock distribution networks corresponding to the control clock signals. The parallel processing circuit unit carries out processes in parallel for each clock distribution network. Each clock distribution network includes the input buffer circuit; a clock buffer circuit connected to the input buffer circuit and placed approximately in a central position of the corresponding circuit block relative to the semiconductor substrate longitudinal direction; and end devices. The clock buffer circuit outputs a control output clock signal to be distributed and supplied to the end devices.Type: GrantFiled: February 24, 2017Date of Patent: March 19, 2019Assignee: RICOH COMPANY, LTD.Inventors: Sho Kamezawa, Tohru Kanno
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Patent number: 10212373Abstract: A semiconductor integrated circuit includes multiple signal processing circuits including a constant current source, a first bias source that generates first bias voltage, a second bias source that generates second bias voltage, a first bias circuit that supplies a first reference current to the first bias source, a second bias circuit that supplies a second reference current to the second bias source, a bias wiring that supplies the first bias voltage and the second bias voltage to a plurality of gates of a transistor that constructs the constant current source, a power source wiring that supplies a power source voltage to each of the first bias source, the second bias source, and the constant current source, a first voltage supplying source that applies a first power source voltage to the power source wiring, and a second voltage supplying that applies a second power source voltage to the power source wiring.Type: GrantFiled: April 26, 2018Date of Patent: February 19, 2019Assignee: RICOH COMPANY, LTD.Inventors: Sho Kamezawa, Tohru Kanno, Yuuya Miyoshi
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Publication number: 20190028075Abstract: A semiconductor integrated circuit including a differential amplifier circuit, a first output circuit, a second output circuit, a selection circuit, and a feedback circuit. The differential amplifier circuit is configured to operate at a first source voltage. The first output circuit is configured to receive an output of the differential amplifier circuit, output a first output, and operate at the first source voltage. The second output circuit is configured to receive an output of the differential amplifier circuit, output a second output, and operate at a second source voltage lower than the first source voltage. The selection circuit is configured to select one of the first output from the first output circuit and the second output from the second output circuit according to an operating phase determined by an external control signal. The feedback circuit is connected between the differential amplifier circuit and the selection circuit.Type: ApplicationFiled: June 27, 2018Publication date: January 24, 2019Inventors: Sho KAMEZAWA, Tohru KANNO
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Publication number: 20180249107Abstract: A semiconductor integrated circuit includes multiple signal processing circuits including a constant current source, a first bias source that generates first bias voltage, a second bias source that generates second bias voltage, a first bias circuit that supplies a first reference current to the first bias source, a second bias circuit that supplies a second reference current to the second bias source, a bias wiring that supplies the first bias voltage and the second bias voltage to a plurality of gates of a transistor that constructs the constant current source, a power source wiring that supplies a power source voltage to each of the first bias source, the second bias source, and the constant current source, a first voltage supplying source that applies a first power source voltage to the power source wiring, and a second voltage supplying that applies a second power source voltage to the power source wiring.Type: ApplicationFiled: April 26, 2018Publication date: August 30, 2018Applicant: RICOH COMPANY, LTD.Inventors: Sho KAMEZAWA, Tohru KANNO, Yuuya MIYOSHI
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Patent number: 9986185Abstract: A semiconductor integrated circuit includes multiple signal processing circuits including a constant current source, a first bias source that generates first bias voltage, a second bias source that generates second bias voltage, a first bias circuit that supplies a first reference current to the first bias source, a second bias circuit that supplies a second reference current to the second bias source, a bias wiring that supplies the first bias voltage and the second bias voltage to a plurality of gates of a transistor that constructs the constant current source, a power source wiring that supplies a power source voltage to each of the first bias source, the second bias source, and the constant current source, a first voltage supplying source that applies a first power source voltage to the power source wiring, and a second voltage supplying that applies a second power source voltage to the power source wiring.Type: GrantFiled: March 2, 2017Date of Patent: May 29, 2018Assignee: RICOH COMPANY, LTD.Inventors: Sho Kamezawa, Tohru Kanno, Yuuya Miyoshi
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Publication number: 20170269630Abstract: A semiconductor integrated circuit on a rectangular semiconductor substrate includes timing generation circuits having the same functions of generating control clock signals to corresponding input buffer circuits based on a control reference clock signal, and a parallel processing circuit unit divided into circuit blocks having equal areas and corresponding to the timing generation circuits. Each circuit block includes clock distribution networks corresponding to the control clock signals. The parallel processing circuit unit carries out processes in parallel for each clock distribution network. Each clock distribution network includes the input buffer circuit; a clock buffer circuit connected to the input buffer circuit and placed approximately in a central position of the corresponding circuit block relative to the semiconductor substrate longitudinal direction; and end devices. The clock buffer circuit outputs a control output clock signal to be distributed and supplied to the end devices.Type: ApplicationFiled: February 24, 2017Publication date: September 21, 2017Applicant: RICOH COMPANY, LTD.Inventors: Sho KAMEZAWA, Tohru KANNO
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Publication number: 20170264844Abstract: A semiconductor integrated circuit includes multiple signal processing circuits including a constant current source, a first bias source that generates first bias voltage, a second bias source that generates second bias voltage, a first bias circuit that supplies a first reference current to the first bias source, a second bias circuit that supplies a second reference current to the second bias source, a bias wiring that supplies the first bias voltage and the second bias voltage to a plurality of gates of a transistor that constructs the constant current source, a power source wiring that supplies a power source voltage to each of the first bias source, the second bias source, and the constant current source, a first voltage supplying source that applies a first power source voltage to the power source wiring, and a second voltage supplying that applies a second power source voltage to the power source wiring.Type: ApplicationFiled: March 2, 2017Publication date: September 14, 2017Applicant: RICOH COMPANY, LTD.Inventors: Sho KAMEZAWA, Tohru KANNO, Yuuya MIYOSHI