Patents by Inventor Sho NAKANISHI

Sho NAKANISHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240106459
    Abstract: According to one embodiment, a compression device includes a substring generator and a match information generator. The substring generator receives generates substrings which are stored in a memory. Byte positions of the substrings are different from each other. The match information generator determines a first string, at least part thereof matching at least part of one of the substrings, and outputs match information. The match information includes a position of the memory storing the first string and a length of the at least part of the first string matching the at least part of one of the substrings.
    Type: Application
    Filed: June 12, 2023
    Publication date: March 28, 2024
    Inventors: Youhei FUKAZAWA, Sho KODAMA, Keiri NAKANISHI
  • Publication number: 20240006487
    Abstract: The semiconductor device has the main surface, the semiconductor substrate having the first impurity region formed on the main surface, the first electrode formed on the main surface having the first impurity region, the insulating film formed on the main surface such that surround the first electrode, the second electrode formed on the insulating film such that spaced apart from the first electrode and annularly surround the first electrode, and the semi-insulating film. The first electrode has the outer peripheral edge portion. The semi-insulating film is continuously formed from on the outer peripheral edge portion to on the second electrode. The outer peripheral edge portion includes the first corner portion. The second electrode has the second corner portion facing the first corner portion. The semi-insulating film on the insulating film is removed between the first corner and the second corner portion.
    Type: Application
    Filed: September 19, 2023
    Publication date: January 4, 2024
    Inventors: Kodai OZAWA, Sho NAKANISHI
  • Publication number: 20230387064
    Abstract: A semiconductor device includes a lead, a semiconductor substrate, a back-surface electrode provided between the semiconductor substrate and the lead, and a solder layer configured to connect the back-surface electrode and the lead. The back-surface electrode includes a silicide layer formed on a back surface of the semiconductor substrate, a bonding layer formed on the lead, a barrier layer formed on the bonding layer, and a stress relaxation layer formed between the silicide layer and the barrier layer. The stress relaxation layer is made of a first metal film containing aluminum as a main component or a second metal film containing gold, silver, or copper as a main component.
    Type: Application
    Filed: March 22, 2023
    Publication date: November 30, 2023
    Inventors: Kodai OZAWA, Sho NAKANISHI
  • Patent number: 11798990
    Abstract: The semiconductor device has the main surface, the semiconductor substrate having the first impurity region formed on the main surface, the first electrode formed on the main surface having the first impurity region, the insulating film formed on the main surface such that surround the first electrode, the second electrode formed on the insulating film such that spaced apart from the first electrode and annularly surround the first electrode, and the semi-insulating film. The first electrode has the outer peripheral edge portion. The semi-insulating film is continuously formed from on the outer peripheral edge portion to on the second electrode. The outer peripheral edge portion includes the first corner portion. The second electrode has the second corner portion facing the first corner portion. The semi-insulating film on the insulating film is removed between the first corner and the second corner portion.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: October 24, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kodai Ozawa, Sho Nakanishi
  • Publication number: 20230275132
    Abstract: An insulating film is formed on a main surface of a semiconductor substrate constituting a semiconductor device so as to cover a field plate portion, a metal pattern thicker than the field plate portion is formed on the insulating film, and a protective film is formed on the insulating film so as to cover the metal pattern. The field plate portion is made of polycrystalline silicon, and the insulating film is composed of a stacked film of one or more silicon nitride films and one or more silicon oxide films.
    Type: Application
    Filed: December 7, 2022
    Publication date: August 31, 2023
    Inventors: Toshiaki IGARASHI, Sho NAKANISHI, Tomoaki UNO, Koshiro YANAI, Masanari MURAYAMA
  • Publication number: 20230268182
    Abstract: Disclosed is a technique for enhancing adhesion between a semiconductor substrate and a back surface electrode covering the back surface thereof. In particular, the enhancing adhesion technique includes: providing a semiconductor substrate SB having a main surface and a back surface opposite to the main surface, the back surface including n-type silicon; forming a first metal layer on the back surface of the semiconductor substrate SB, the first metal layer including nickel and vanadium which has a thermal diffusion coefficient smaller than that of nickel; performing a heat treatment to the semiconductor substrate to react silicon contained in the semiconductor substrate with nickel contained in the first metal layer to form a NiSiV layer in contact with the back surface of the semiconductor substrate; and forming a second metal including titanium on the NiSiV layer.
    Type: Application
    Filed: November 23, 2022
    Publication date: August 24, 2023
    Inventors: Sho NAKANISHI, Kodai OZAWA
  • Publication number: 20220140077
    Abstract: The semiconductor device has the main surface, the semiconductor substrate having the first impurity region formed on the main surface, the first electrode formed on the main surface having the first impurity region, the insulating film formed on the main surface such that surround the first electrode, the second electrode formed on the insulating film such that spaced apart from the first electrode and annularly surround the first electrode, and the semi-insulating film. The first electrode has the outer peripheral edge portion. The semi-insulating film is continuously formed from on the outer peripheral edge portion to on the second electrode. The outer peripheral edge portion includes the first corner portion. The second electrode has the second corner portion facing the first corner portion. The semi-insulating film on the insulating film is removed between the first corner and the second corner portion.
    Type: Application
    Filed: November 1, 2021
    Publication date: May 5, 2022
    Inventors: Kodai OZAWA, Sho NAKANISHI
  • Patent number: 10680072
    Abstract: The reliability of resistive field plate part-containing semiconductor device is improved. In peripheral region of semiconductor chip, the outer circumference end of internal circulation wire is separated from outer circumference end of first conductor pattern of resistive field plate part toward element region. Inner circumference end of external circulation wire is separated from inner circumference end of second conductor pattern of resistive field plate part toward outer circumference of the chip. First conductor pattern of resistive field plate part is partially extended to over thin insulation film to form first lead-out part, and internal circulation wire and first lead-out part of first conductor pattern are electrically coupled via first coupling hole.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: June 9, 2020
    Assignee: RENESAS ELECTRONICS COPORATION
    Inventor: Sho Nakanishi
  • Patent number: 10290727
    Abstract: A performance of a semiconductor device including an RC-IGBT is improved. An AlNiSi layer (a layer containing aluminum (Al), nickel (Ni), and silicon (Si)) is formed between a back surface of a semiconductor substrate and a back surface electrode. Thus, a favorable ohmic junction can be obtained between the back surface electrode and an N+-type layer constituting a cathode region in an embedded diode, and a favorable ohmic junction can be obtained between the back surface electrode and a P-type layer constituting a collector region in an IGBT. The AlNiSi layer contains 10 at % or more of each of the aluminum (Al), the nickel (Ni), and the silicon (Si).
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: May 14, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Sho Nakanishi, Yuji Fujii
  • Publication number: 20190097002
    Abstract: The reliability of resistive field plate part-containing semiconductor device is improved. In peripheral region of semiconductor chip, the outer circumference end of internal circulation wire is separated from outer circumference end of first conductor pattern of resistive field plate part toward element region. Inner circumference end of external circulation wire is separated from inner circumference end of second conductor pattern of resistive field plate part toward outer circumference of the chip. First conductor pattern of resistive field plate part is partially extended to over thin insulation film to form first lead-out part, and internal circulation wire and first lead-out part of first conductor pattern are electrically coupled via first coupling hole.
    Type: Application
    Filed: July 25, 2018
    Publication date: March 28, 2019
    Inventor: Sho NAKANISHI
  • Patent number: 10115795
    Abstract: To provide a highly reliable semiconductor device having both an improved breakdown voltage and a reduced withstand voltage leakage current. An intermediate resistive field plate is comprised of a first intermediate resistive field plate coupled, at one end thereof, to an inner-circumferential-side resistive field plate and, at the other end, to an outer-circumferential-side resistive field plate and a plurality of second intermediate resistive field plates. The first intermediate resistive field plate has a planar pattern that is equipped with a plurality of first portions separated from each other in a first direction connecting the inner-circumferential resistive field plate to the outer-circumferential-side resistive field plate and linearly extending in a second direction orthogonal to the first direction, and repeats reciprocation along the second direction.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: October 30, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Sho Nakanishi
  • Patent number: 9768286
    Abstract: In a back surface hole injection type diode, by more effectively securing the effect of hole injection from the back surface of a semiconductor substrate, the performance of a semiconductor device is improved. In the semiconductor device, in a diode formed of a P-N junction including an anode P-type layer formed in the main surface of a semiconductor substrate and a back surface N+-type layer formed in the back surface of the semiconductor substrate, a back surface P+-type layer is formed in the back surface, and a surface P+-type layer is formed in the main surface right above the back surface P+-type layer to thereby promote the effect of hole injection from the back surface.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: September 19, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Sho Nakanishi
  • Publication number: 20170229551
    Abstract: To provide a highly reliable semiconductor device having both an improved breakdown voltage and a reduced withstand voltage leakage current. An intermediate resistive field plate is comprised of a first intermediate resistive field plate coupled, at one end thereof, to an inner-circumferential-side resistive field plate and, at the other end, to an outer-circumferential-side resistive field plate and a plurality of second intermediate resistive field plates. The first intermediate resistive field plate has a planar pattern that is equipped with a plurality of first portions separated from each other in a first direction connecting the inner-circumferential resistive field plate to the outer-circumferential-side resistive field plate and linearly extending in a second direction orthogonal to the first direction, and repeats reciprocation along the second direction.
    Type: Application
    Filed: February 2, 2017
    Publication date: August 10, 2017
    Inventor: Sho NAKANISHI
  • Publication number: 20170207331
    Abstract: A performance of a semiconductor device including an RC-IGBT is improved. An AlNiSi layer (a layer containing aluminum (Al), nickel (Ni), and silicon (Si)) is formed between a back surface of a semiconductor substrate and a back surface electrode. Thus, a favorable ohmic junction can be obtained between the back surface electrode and an N+-type layer constituting a cathode region in an embedded diode, and a favorable ohmic junction can be obtained between the back surface electrode and a P-type layer constituting a collector region in an IGBT. The AlNiSi layer contains 10 at % or more of each of the aluminum (Al), the nickel (Ni), and the silicon (Si).
    Type: Application
    Filed: January 12, 2017
    Publication date: July 20, 2017
    Inventors: Sho NAKANISHI, Yuji FUJII
  • Publication number: 20160359028
    Abstract: In a back surface hole injection type diode, by more effectively securing the effect of hole injection from the back surface of a semiconductor substrate, the performance of a semiconductor device is improved. In the semiconductor device, in a diode formed of a P-N junction including an anode P-type layer formed in the main surface of a semiconductor substrate and a back surface N+-type layer formed in the back surface of the semiconductor substrate, a back surface P+-type layer is formed in the back surface, and a surface P+-type layer is formed in the main surface right above the back surface P+-type layer to thereby promote the effect of hole injection from the back surface.
    Type: Application
    Filed: August 17, 2016
    Publication date: December 8, 2016
    Inventor: Sho NAKANISHI
  • Patent number: 9449926
    Abstract: In a back surface hole injection type diode, by more effectively securing the effect of hole injection from the back surface of a semiconductor substrate, the performance of a semiconductor device is improved. In the semiconductor device, in a diode formed of a P-N junction including an anode P-type layer formed in the main surface of a semiconductor substrate and a back surface N+-type layer formed in the back surface of the semiconductor substrate, a back surface P+-type layer is formed in the back surface, and a surface P+-type layer is formed in the main surface right above the back surface P+-type layer to thereby promote the effect of hole injection from the back surface.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: September 20, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Sho Nakanishi
  • Publication number: 20160163654
    Abstract: In a back surface hole injection type diode, by more effectively securing the effect of hole injection from the back surface of a semiconductor substrate, the performance of a semiconductor device is improved. In the semiconductor device, in a diode formed of a P-N junction including an anode P-type layer formed in the main surface of a semiconductor substrate and a back surface N+-type layer formed in the back surface of the semiconductor substrate, a back surface P+-type layer is formed in the back surface, and a surface P+-type layer is formed in the main surface right above the back surface P+-type layer to thereby promote the effect of hole injection from the back surface.
    Type: Application
    Filed: November 9, 2015
    Publication date: June 9, 2016
    Inventor: Sho NAKANISHI