Patents by Inventor Sho Osada

Sho Osada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7998801
    Abstract: Decrease of the off-state current, increase of the on-state current, and reduction of variations of electrical characteristics. A method for manufacturing a channel-etched inversed staggered thin film transistor includes the following steps: removing, by first dry-etching, a part of a semiconductor layer including an impurity element which imparts one conductivity type, which is exposed from the source and drain electrodes, and partially a part of an amorphous semiconductor layer just below and in contact with the part of the semiconductor layer; removing, by second dry-etching, partially the part of the amorphous semiconductor layer which is exposed by the first dry-etching; and performing plasma treatment on the surface of the part of the amorphous semiconductor layer which is exposed by the second dry-etching so that an altered layer is formed.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: August 16, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Motomu Kurata, Sho Osada
  • Publication number: 20100099226
    Abstract: Decrease of the off-state current, increase of the on-state current, and reduction of variations of electrical characteristics. A method for manufacturing a channel-etched inversed staggered thin film transistor includes the following steps: removing, by first dry-etching, a part of a semiconductor layer including an impurity element which imparts one conductivity type, which is exposed from the source and drain electrodes, and partially a part of an amorphous semiconductor layer just below and in contact with the part of the semiconductor layer; removing, by second dry-etching, partially the part of the amorphous semiconductor layer which is exposed by the first dry-etching; and performing plasma treatment on the surface of the part of the amorphous semiconductor layer which is exposed by the second dry-etching so that an altered layer is formed.
    Type: Application
    Filed: April 16, 2009
    Publication date: April 22, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shinya SASAGAWA, Motomu KURATA, Sho OSADA