Abstract: The present invention relates to the development of a device, Cognitive Communication Hub (CCH) that combines multiple and hybrid physical layers to collaborate and establish a unified network. The heterogeneous network so formed supports a whole range of bandwidth and spectrum while providing quality of service and class of service. The routing algorithm of the device is designed to explore the best route that can optimally use hybrid networking technologies to make a connection. The device has multiple interfaces and acts in an adhoc fashion. It forms multiple parallel data paths between source and destination and hence provides fault tolerance as a break down in one path does not disconnect end to end connection.

Abstract: The systems and methods of the present invention for multi-layer feature based biometric matching comprise of distributed acquisition sites for acquiring the biometric features and central processing servers, where the biometric matching may be performed. The proposed systems and methods may be run at the central processing servers of any large biometric matching system, and may comprise a plurality of scalable processing layers that coexist to perform high-density matching operations in reduced time. The system for matching biometric features may comprise a user domain, a controller domain, a matching domain, the user domain communicates with the controller domain, and the controller domain communicates with the matching domain.

Abstract: The present invention relates to the development of a device, Cognitive Communication Hub (CCH) that combines multiple and hybrid physical layers to collaborate and establish a unified network. The heterogeneous network so formed supports a whole range of bandwidth and spectrum while providing quality of service and class of service. The routing algorithm of the device is designed to explore the best route that can optimally use hybrid networking technologies to make a connection. The device has multiple interfaces and acts in an adhoc fashion. It forms multiple parallel data paths between source and destination and hence provides fault tolerance as a break down in one path does not disconnect end to end connection.

Abstract: The present invention uses pseudorandom sequence to develop a strategy for the parallel communication of frequency hopped tactical radios. For this purpose, both time division multiplexing and frequency division multiplexing are used.

Abstract: The present invention relates to digital signal processors with an integrated module configured to compute a Coordinate Rotation Digital Computer (CORDIC) in a pipeline. The pipelined module can advantageously complete computation of one CORDIC computation for each clock pulse applied to the CORDIC module, thereby providing a CORDIC computation for each clock pulse. One embodiment advantageously computes a first portion of a computation with a lookup table and a second portion in accordance with a CORDIC algorithm. Advantageously, data in a CORDIC pipeline is automatically advanced in response to read instructions and can be automatically advanced from the beginning of the pipeline to the end of the pipeline to reinitialize the pipeline. This allows information to be retrieved from the CORDIC pipeline with relatively little overhead. The automatic starting and stopping of the CORDIC pipeline advantageously allows the retrieval of computations from efficient pipeline architectures on an as-needed basis.

Abstract: The present invention is a system on chip architecture having scalable, distributed processing and memory capabilities through a plurality of processing layers. In a preferred embodiment, a distributed processing layer processor comprises a plurality of processing layers, a processing layer controller, and a central direct memory access controller. The processing layer controller manages the scheduling of tasks and distribution of processing tasks to each processing layer. Within each processing layer, a plurality of pipelined processing units (PUs), specially designed for conducting a defined set of processing tasks, are in communication with a plurality of program memories and data memories. One application of the present invention is in a media gateway that is designed to enable the communication of media across circuit switched and packet switched networks.

Abstract: The present invention relates to digital signal processors with an integrated module configured to compute a Coordinate Rotation Digital Computer (CORDIC) in a pipeline. The pipelined module can advantageously complete computation of one CORDIC computation for each clock pulse applied to the CORDIC module, thereby providing a CORDIC computation for each clock pulse. One embodiment advantageously computes a first portion of a computation with a lookup table and a second portion in accordance with a CORDIC algorithm. Advantageously, data in a CORDIC pipeline is automatically advanced in response to read instructions and can be automatically advanced from the beginning of the pipeline to the end of the pipeline to reinitialize the pipeline. This allows information to be retrieved from the CORDIC pipeline with relatively little overhead The automatic starting and stopping of the CORDIC pipeline advantageously allows the retrieval of computations from efficient pipeline architectures on an as-needed basis.

Abstract: The present invention relates to digital signal processors with an integrated module configured to compute a Coordinate Rotation Digital Computer (CORDIC) in a pipeline. The pipelined module can advantageously complete computation of one CORDIC computation for each clock pulse applied to the CORDIC module, thereby providing a CORDIC computation for each clock pulse. One embodiment advantageously computes a first portion of a computation with a lookup table and a second portion in accordance with a CORDIC algorithm. Advantageously, data in a CORDIC pipeline is automatically advanced in response to read instructions and can be automatically advanced from the beginning of the pipeline to the end of the pipeline to reinitialize the pipeline. This allows information to be retrieved from the CORDIC pipeline with relatively little overhead. The automatic starting and stopping of the CORDIC pipeline advantageously allows the retrieval of computations from efficient pipeline architectures on an as-needed basis.

Abstract: The invention is related to methods and apparatus that decode convolutionally encoded data, including trellis-coded modulation (TCM) systems. One embodiment of the invention shares a memory device with a main processor, such as a microprocessor or a DSP, and advantageously relieves the main processor of the relatively time-consuming task of decoding the convolutionally encoded data. This frees up the main processor to execute other tasks. One embodiment of the invention includes a micro-coded state machine that can be programmed to control the decoding of the convolutional codes.

Abstract: The present application discloses an instruction format for storing multiple microprocessor instructions as one combined instruction. The instruction format includes a combination opcode field for storing a combination opcode that identifies a combination of the multiple instructions. The application also discloses an instruction format that uses prefix fields to specify the destination functional block for each combined instruction stored in an execute packet. A compiler program or an assembler program obtains from a table a combination opcode that corresponds to a combination of the multiple instructions. The table stores combination opcodes and their corresponding combinations of instructions. The compiler program or assembler program then assigns the found combination opcode to an opcode field of the combined instruction. In a trivial scenario, a single instruction can also be stored as a combined instruction.

Abstract: A method for scheduling computation operations on a very long instruction word processor to achieve an optimal iteration period for a cyclic algorithm uses a flow graph to aid in scheduling instructions. In the flow graph, each computation operation appears as a separate node, and the edges between nodes represent data dependencies. The flow graph is transformed into machine-readable data for use in an integer linear program. The machine-readable data expresses equations and constraints associated with the optimal iteration period of the algorithm implemented on a processor having a plurality of types of functional units. The equations and constraints comprise an objective function to be minimized, a set of operation precedent constraints, job completion constraints, iteration period constraints and functional unit constraints. The nature of the equations and constraints are modified based upon processor architecture.

Abstract: The present invention relates to digital signal processors with an integrated module configured to compute a Coordinate Rotation Digital Computer (CORDIC) in a pipeline. The pipelined module can advantageously complete computation of one CORDIC computation for each clock pulse applied to the CORDIC module, thereby providing a CORDIC computation for each clock pulse. One embodiment advantageously computes a first portion of a computation with a lookup table and a second portion in accordance with a CORDIC algorithm. Advantageously, data in a CORDIC pipeline is automatically advanced in response to read instructions and can be automatically advanced from the beginning of the pipeline to the end of the pipeline to reinitialize the pipeline. This allows information to be retrieved from the CORDIC pipeline with relatively little overhead. The automatic starting and stopping of the CORDIC pipeline advantageously allows the retrieval of computations from efficient pipeline architectures on an as-needed basis.

Abstract: The invention is related to methods and apparatus that decode convolutionally encoded data, including trellis-coded modulation (TCM) systems. One embodiment of the invention shares a memory device with a main processor, such as a microprocessor or a DSP, and advantageously relieves the main processor of the relatively time-consuming task of decoding the convolutionally encoded data. This frees up the main processor to execute other tasks. One embodiment of the invention includes a micro-coded state machine that can be programmed to control the decoding of the convolutional codes.