Abstract: A memory cell includes a first electrode, a second electrode, and phase-change material including a first portion contacting the first electrode, a second portion contacting the second electrode, and a third portion between the first portion and the second portion. A width of the third portion is less than a width of the first portion and a width of the second portion.

Abstract: An integrated circuit is disclosed. One embodiment includes a first diode, a second diode, and a semiconductor line coupled to the first diode and the second diode. The line includes a first silicide region between the first diode and the second diode.

Abstract: A phase change memory cell is disclosed. The phase change memory cell includes a first thin film spacer and a second thin film spacer. The first thin film spacer defines a sub-lithographic dimension and is electrically coupled to a first electrode. The second thin film spacer defines a sub-lithographic dimension and is electrically coupled between a second electrode and the first thin film spacer. In this regard, the phase change memory cell is formed at a boundary where the first thin film spacer electrically contacts the second thin film spacer.

Abstract: An integrated circuit is disclosed. One embodiment includes a first diode, a second diode, and a semiconductor line coupled to the first diode and the second diode. The line includes a first silicide region between the first diode and the second diode.

Abstract: Targets or test structures used for measurements in semiconductor devices having long lines exceeding design rule limitations are divided into segments. In one embodiment, the segments have periodicity in a direction parallel to the length of the lines. In another embodiment, the segments of test structures in adjacent lines do not have periodicity in a direction parallel to the length of the lines. The lack of periodicity is achieved by staggering segments of substantially equal lengths in adjacent lines, or by dividing the lines into segments having unequal lengths. The test structures may be formed in scribe line regions or die regions of a semiconductor wafer.

Abstract: A phase change memory cell is disclosed. The phase change memory cell includes a first thin film spacer and a second thin film spacer. The first thin film spacer defines a sub-lithographic dimension and is electrically coupled to a first electrode. The second thin film spacer defines a sub-lithographic dimension and is electrically coupled between a second electrode and the first thin film spacer. In this regard, the phase change memory cell is formed at a boundary where the first thin film spacer electrically contacts the second thin film spacer.

Abstract: A phase change memory cell is disclosed. The phase change memory cell includes a first thin film spacer and a second thin film spacer. The first thin film spacer defines a sub-lithographic dimension and is electrically coupled to a first electrode. The second thin film spacer defines a sub-lithographic dimension and is electrically coupled between a second electrode and the first thin film spacer. In this regard, the phase change memory cell is formed at a boundary where the first thin film spacer electrically contacts the second thin film spacer.

Abstract: A system includes a non-contacting optical measurement instrument and a controller. The non-contacting optical measurement instrument is configured to obtain a measurement of a phase-change material. The controller is configured to determine a resistivity of the phase-change material based on the measurement.

Abstract: The properties of features formed in a substrate are measured. Lenslet array illumination is used to illuminate regions of a substrate so that the features of interest occupy a greater proportion of the illuminated area. The signal-to-noise ratio of the measurement signal is therefore increased, and the sensitivity of the measurement is thus improved.

Abstract: A method and mask to improve measurement of alignment marks is disclosed. An exemplary embodiment of the invention includes a resist mask with a patterned alignment mark comprising an assemblage of features whose spacing is smaller than the wavelength of light used to measure the alignment. In a preferred embodiment, an alignment mark patterning process alters the appearance of the alignment mark and renders an enhanced contrast with the substrate background.

Abstract: An alignment or overlay mark with improved signal to noise ratio is disclosed. Improved signal-to-noise ratio results in greater depth of focus, thus improving the performance of the alignment mark. The alignment mark comprises a zone plate having n concentric alternating opaque and non-opaque rings. Light diffracted by either the odd or even rings are cancelled while light diffracted by the other of the odd or even rings are added.

Abstract: There is provided a method for measuring planarized features on a wafer of a semiconductor device. The planarized features on the wafer are illuminated. A reflected light beam with respect to the planarized features is detected. Optical characteristics of the reflected light beam are analyzed to determine information corresponding to the planarized features. Preferably, the analyzing step maximizes an analysis of the optical characteristics based upon a simplified geometry of the planarized features with respect to a geometry of similar, un-planarized features. Moreover, preferably, the analyzing step maximizes an analysis of the optical characteristics based upon a reduction in complexity of the planarized features due to a similarity in refractive indexes corresponding to a bulk silicon substrate and a poly silicon fill of the semiconductor device.

Abstract: An alignment or overlay mark with improved signal to noise ratio is disclosed. Improved signal-to-noise ratio results in greater depth of focus, thus improving the performance of the alignment mark. The alignment mark comprises a zone plate having n concentric alternating opaque and non-opaque rings. Light diffracted by either the odd or even rings are cancelled while light diffracted by the other of the odd or even rings are added.

Abstract: A wavefront sensing tool, such as a Shack-Hartmann detector, detects alignment features in a semiconductor wafer that might otherwise be undetectable using conventional optical tools, such as a microscope. This is particularly advantageous for alignment features formed in photoresist with a height that is less than one fourth the illuminating light's wavelength. The wavefront sensing tool can be used in conjunction with conventional optical tools and a composite alignment image can be formed from the two tools. For higher sensitivity, the light reflected off the wafer can be magnified, with e.g. a telescopic lens, prior to impinging upon the wavefront sensing tool. The composite image can be generated by one or both of the tools or by a computer coupled to the tools.

Abstract: A method of measuring the rate of etching of trenches on a substrate using interferometry is provided. The method comprises transmitting onto the substrate incident electromagnetic radiation having a wavelength above the wavelength at which the trenches act as waveguides for the radiation; collecting reflected electromagnetic radiation from the substrate; detecting a repetitive pattern of maximum intensities and minimum intensities of the reflected electromagnetic radiation during the etching; and determining the rate of etching based upon the wavelength of the incident electromagnetic radiation and the time period of the pattern.

Abstract: A method of measuring the rate of etching of trenches on a substrate using interferometry is provided. The method comprises transmitting onto the substrate incident electromagnetic radiation having a wavelength above the wavelength at which the trenches act as waveguides for the radiation; collecting reflected electromagnetic radiation from the substrate; detecting a repetitive pattern of maximum intensities and minimum intensities of the reflected electromagnetic radiation during the etching; and determining the rate of etching based upon the wavelength of the incident electromagnetic radiation and the time period of the pattern.

Abstract: The present invention provides a method of enabling measurement access to small integrated circuit features that comprises selecting a feature of an integrated circuit on a wafer and providing access to the selected feature by removing a portion of the integrated circuit adjacent to the feature, thereby preserving the wafer.

Abstract: A wavefront sensing tool, such as a Shack-Hartmann detector, detects alignment features in a semiconductor wafer that might otherwise be undetectable using conventional optical tools, such as microscope. This is particularly advantageous for alignment features formed in photoresist with a height that is less than one fourth the illuminating light's wavelength. The wavefront sensing tool can be used in conjunction with conventional optical tools and a composite alignment image can be formed from the two tools. For higher sensitivity, the light reflected off the wafer can be magnified, with e.g. a telescopic lens, prior to impinging upon the wavefront sensing tool. The composite image can be generated by one or both the tools or by a computer coupled to the tools.

Abstract: There is provided a method for measuring planarized features on a wafer of a semiconductor device. The planarized features on the wafer are illuminated. A reflected light beam with respect to the planarized features is detected. Optical characteristics of the reflected light beam are analyzed to determine information corresponding to the planarized features. Preferably, the analyzing step maximizes an analysis of the optical characteristics based upon a simplified geometry of the planarized features with respect to a geometry of similar, un-planarized features. Moreover, preferably, the analyzing step maximizes an analysis of the optical characteristics based upon a reduction in complexity of the planarized features due to a similarity in refractive indexes corresponding to a bulk silicon substrate and a poly silicon fill of the semiconductor device.