Abstract: A low cost technique for detecting defects in photolithography processes in a submicron integrated circuit manufacturing environment combines use of a reusable test wafer with in-line processing to monitor defects using a pattern comparator system. A reusable test wafer having an oxide layer overlying a silicon substrate and having a thickness corresponding to a minimum reflectance for an exposure wavelength used for photolithography is patterned using a prescribed photolithographic fabrication process to form a repetitive pattern according to a prescribed design product rule. The pattern is formed using a reticle having a repetitive pattern array with a similar design rule as the product to be developed by the lithography processes. The patterned test wafer is then inspected using image-based inspection techniques, where the image has high resolution pixels of preferably 0.25 microns per pixel.