Patents by Inventor Shobhit Singhal
Shobhit Singhal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240134548Abstract: A memory system includes a main memory, an auxiliary memory, a redundancy circuit, an extension control terminal, and a multiplexer. The main memory has a line width, and includes a write data input. The auxiliary memory has the same line width as the main memory, and includes a write data input. The redundancy circuit includes and input and an output. The input is coupled to the write data input of the main memory. The multiplexer includes a first input, a second input, a control input, and an output. The first input is coupled to the write data input of the main memory. The second input is coupled to the output of the redundancy circuit. The control input is coupled to the extension control terminal. The output of the multiplexer is coupled to the write data input of the auxiliary memory.Type: ApplicationFiled: December 20, 2023Publication date: April 25, 2024Inventors: Shobhit SINGHAL, Ruchi SHANKAR, Sverre BRUBAEK, Praveen KUMAR N
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Patent number: 11899954Abstract: A memory system includes a main memory, an auxiliary memory, a redundancy circuit, an extension control terminal, and a multiplexer. The main memory has a line width, and includes a write data input. The auxiliary memory has the same line width as the main memory, and includes a write data input. The redundancy circuit includes and input and an output. The input is coupled to the write data input of the main memory. The multiplexer includes a first input, a second input, a control input, and an output. The first input is coupled to the write data input of the main memory. The second input is coupled to the output of the redundancy circuit. The control input is coupled to the extension control terminal. The output of the multiplexer is coupled to the write data input of the auxiliary memory.Type: GrantFiled: February 2, 2022Date of Patent: February 13, 2024Assignee: Texas Instruments IncorporatedInventors: Shobhit Singhal, Ruchi Shankar, Sverre Brubaek, Praveen Kumar N
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Publication number: 20230396550Abstract: Interconnect systems and method of operating such are disclosed. A plurality of nodes coupled via a packet transport path form an interconnect and the nodes provide ingress points to the interconnect for a plurality of packet sources. A central controller holds permitted rate indications for each of the plurality of packet sources, in accordance with which each packet source sends packets via the interconnect. The nodes each respond to packet collision event at that node by sending a collision report to the central controller. In response the central controller, in respect of a collision pair of packet sources associated with the packet collision, decreases the permitted rate indication corresponding to a packet source of the collision pair of packet sources which currently has the higher permitted rate indication. Periodically the permitted rate indications of all of the packet sources are increased, subject to a maximum permitted rate indication for each.Type: ApplicationFiled: June 1, 2022Publication date: December 7, 2023Inventors: Andrew John TURNER, Shobhit SINGHAL, Alex James WAUGH, Inaki Abadia OSTA
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Patent number: 11784941Abstract: An apparatus and method for operating a ring interconnect are disclosed. The ring interconnect has a plurality of nodes that are used to connect to associated components, and is arranged to transport a plurality of slots around the ring interconnect between the nodes in order to transfer items of traffic allocated into those slots between components connected to the nodes. For each item of traffic, one of the components acts as a source to allocate that item of traffic into a slot, and another components acts as destination to seek to remove that item of traffic from the slot. In a default mode of operation, the ring interconnect is arranged to allow all of the slots to be available for transfer of any items of traffic.Type: GrantFiled: July 13, 2021Date of Patent: October 10, 2023Assignee: Arm LimitedInventors: Alex James Waugh, Andrew John Turner, Shobhit Singhal
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Publication number: 20230244396Abstract: A memory system includes a main memory, an auxiliary memory, a redundancy circuit, an extension control terminal, and a multiplexer. The main memory has a line width, and includes a write data input. The auxiliary memory has the same line width as the main memory, and includes a write data input. The redundancy circuit includes and input and an output. The input is coupled to the write data input of the main memory. The multiplexer includes a first input, a second input, a control input, and an output. The first input is coupled to the write data input of the main memory. The second input is coupled to the output of the redundancy circuit. The control input is coupled to the extension control terminal. The output of the multiplexer is coupled to the write data input of the auxiliary memory.Type: ApplicationFiled: February 2, 2022Publication date: August 3, 2023Inventors: Shobhit SINGHAL, Ruchi SHANKAR, Sverre BRUBAEK, Praveen KUMAR N
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Patent number: 11700336Abstract: Aspects of the disclosure provide for a circuit, in some examples, including a storage element, a co-processor, and a telemetry sequencer coupled to the storage element and the co-processor. The telemetry sequencer is configured to implement a digital state machine to receive configuration information indicating a type of telemetry data for generation, retrieve operations and operands, where the operations and the operands define a sequential series of actions for execution to generate the telemetry data, drive the co-processor with the operations and the operands by passing some of the operations and some of the operands to the co-processor for processing by the co-processor, receive, from the co-processor, and store an intermediate output of the series of actions as the telemetry data in a first format, and receive, from the co-processor, and store a final output of the series of actions as the telemetry data in a second format.Type: GrantFiled: February 4, 2022Date of Patent: July 11, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shobhit Singhal, Vikas Lakhanpal, Preetam Tadeparthy
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Publication number: 20230197143Abstract: A static random-access memory (SRAM) includes a SRAM cell module, comprising a plurality of SRAM cell partitions, and an initialization register, containing data configured to control initialization of at least some of the plurality of partitions during an initialization phase. The SRAM also includes a control module coupled with the SRAM cell module and the initialization register, configured to read the initialization register during the initialization phase, and to selectively initialize a portion of the plurality of SRAM cell partitions, based at least in part on the data contained within the initialization register.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Inventors: Ruchi Shankar, Shobhit Singhal, Sverre Brubæk, Praveen Kumar Narayanan
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Publication number: 20230076376Abstract: A microcontroller is provided and comprises a central repository, a processing device, and a firewall. Rule repository memory in the central repository stores one or more access rules defining an access permission of a software context to one or more target resources of the microcontroller. The firewall receives a bus transaction initiated based on an instruction and determines whether any access rule stored in memory of the firewall defines the access permission of the software context to a destination resource. If no access rule stored in the firewall memory defines the access permission, the firewall communicates a miss query condition to the central repository. The central repository searches the rule repository memory for an access rule defining the access permission of the software context to the destination resource, and if a related access rule is found, the related access rule is stored in the firewall memory.Type: ApplicationFiled: September 9, 2021Publication date: March 9, 2023Inventors: Robin O. Hoel, Eric Peeters, Prithvi Shankar Yeyyadi Anantha, Aniruddha Periyapatna Nagendra, Shobhit Singhal, Ruchi Shankar, Prachi Mishra
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Publication number: 20230021078Abstract: An apparatus and method for operating a ring interconnect are disclosed. The ring interconnect has a plurality of nodes that are used to connect to associated components, and is arranged to transport a plurality of slots around the ring interconnect between the nodes in order to transfer items of traffic allocated into those slots between components connected to the nodes. For each item of traffic, one of the components acts as a source to allocate that item of traffic into a slot, and another components acts as destination to seek to remove that item of traffic from the slot. In a default mode of operation, the ring interconnect is arranged to allow all of the slots to be available for transfer of any items of traffic.Type: ApplicationFiled: July 13, 2021Publication date: January 19, 2023Inventors: Alex James WAUGH, Andrew John Turner, Shobhit Singhal
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Patent number: 11411387Abstract: An over/under voltage protection circuit includes a voltage input terminal, a digital-to analog converter, a comparator, and a control circuit. The comparator includes a first input coupled to an output of the digital-to-analog converter, and a second input coupled to the voltage input terminal. The control circuit includes an output coupled to an input of the digital-to-analog converter, and an input coupled to an output of the comparator. The control circuit is configured to set the digital-to-analog converter to generate an overvoltage fault threshold responsive to the output of the comparator indicating that voltage of a signal at the voltage input terminal exceeds a threshold currently generated by the digital-to-analog converter.Type: GrantFiled: October 21, 2019Date of Patent: August 9, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mayank Jain, Preetam Tadeparthy, Rohit Narula, Shobhit Singhal
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Publication number: 20220159128Abstract: Aspects of the disclosure provide for a circuit, in some examples, including a storage element, a co-processor, and a telemetry sequencer coupled to the storage element and the co-processor. The telemetry sequencer is configured to implement a digital state machine to receive configuration information indicating a type of telemetry data for generation, retrieve operations and operands, where the operations and the operands define a sequential series of actions for execution to generate the telemetry data, drive the co-processor with the operations and the operands by passing some of the operations and some of the operands to the co-processor for processing by the co-processor, receive, from the co-processor, and store an intermediate output of the series of actions as the telemetry data in a first format, and receive, from the co-processor, and store a final output of the series of actions as the telemetry data in a second format.Type: ApplicationFiled: February 4, 2022Publication date: May 19, 2022Inventors: Shobhit Singhal, Vikas Lakhanpal, Preetam Tadeparthy
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Patent number: 11283935Abstract: Aspects of the disclosure provide for a circuit, in some examples, including a storage element, a co-processor, and a telemetry sequencer coupled to the storage element and the co-processor. The telemetry sequencer is configured to implement a digital state machine to receive configuration information indicating a type of telemetry data for generation, retrieve operations and operands, where the operations and the operands define a sequential series of actions for execution to generate the telemetry data, drive the co-processor with the operations and the operands by passing some of the operations and some of the operands to the co-processor for processing by the co-processor, receive, from the co-processor, and store an intermediate output of the series of actions as the telemetry data in a first format, and receive, from the co-processor, and store a final output of the series of actions as the telemetry data in a second format.Type: GrantFiled: December 30, 2019Date of Patent: March 22, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shobhit Singhal, Vikas Lakhanpal, Preetam Tadeparthy
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Publication number: 20210203786Abstract: Aspects of the disclosure provide for a circuit, in some examples, including a storage element, a co-processor, and a telemetry sequencer coupled to the storage element and the co-processor. The telemetry sequencer is configured to implement a digital state machine to receive configuration information indicating a type of telemetry data for generation, retrieve operations and operands, where the operations and the operands define a sequential series of actions for execution to generate the telemetry data, drive the co-processor with the operations and the operands by passing some of the operations and some of the operands to the co-processor for processing by the co-processor, receive, from the co-processor, and store an intermediate output of the series of actions as the telemetry data in a first format, and receive, from the co-processor, and store a final output of the series of actions as the telemetry data in a second format.Type: ApplicationFiled: December 30, 2019Publication date: July 1, 2021Inventors: Shobhit SINGHAL, Vikas LAKHANPAL, Preetam TADEPARTHY
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Publication number: 20210119435Abstract: An over/under voltage protection circuit includes a voltage input terminal, a digital-to analog converter, a comparator, and a control circuit. The comparator includes a first input coupled to an output of the digital-to-analog converter, and a second input coupled to the voltage input terminal. The control circuit includes an output coupled to an input of the digital-to-analog converter, and an input coupled to an output of the comparator. The control circuit is configured to set the digital-to-analog converter to generate an overvoltage fault threshold responsive to the output of the comparator indicating that voltage of a signal at the voltage input terminal exceeds a threshold currently generated by the digital-to-analog converter.Type: ApplicationFiled: October 21, 2019Publication date: April 22, 2021Inventors: Mayank JAIN, Preetam TADEPARTHY, Rohit NARULA, Shobhit SINGHAL
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Patent number: 8942333Abstract: Apparatuses and methods for phase aligning at least two clocks used by respective first and second circuitry systems, such as a memory controller and a DDR PHY interface in a system on a chip system. A first circuit samples a phase of a first clock used by the first circuitry system, and then a delay circuit selectively delays a second clock used by the second circuitry system and sets a delayed timing of the second clock. To economize resources and reduce chip area, a logic circuit receives the sampled phase of the first clock, determines which delayed timing matches timing of the sampled phase, and sets the delay circuit to a fixed delayed timing corresponding to the delayed timing that matches the sampled phase. Thus, phase alignment of the two clocks is achieved with fewer resources.Type: GrantFiled: November 12, 2012Date of Patent: January 27, 2015Assignee: Texas Instruments IncorporatedInventors: Arvind Kumar, Shobhit Singhal, Vikas Lakhanpal, Kalpesh Amrutlal Shah
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Patent number: 8737161Abstract: A system is provided for use with a DRAM, a DQS signal provider, a clock signal provider, a DQS line and a clock line. The DQS line can provide the DQS signal from the DQS signal provider to the DRAM. The clock line can provide the clock signal from the clock signal provider to the DRAM. The system includes a clock delay determining portion, a DQS delay determining portion, and adjustment portion and a controlling portion. The clock delay determining portion can determine a clock delay. The DQS delay determining portion can determine a DQS delay. The adjustment portion can generate an adjustment value based on the clock delay and the DQS delay. The controlling portion can instruct the DQS signal provider to adjust a time of providing a second DQS signal based on the adjustment value, wherein the clock delay is less than the DQS delay.Type: GrantFiled: February 15, 2013Date of Patent: May 27, 2014Assignee: Texas Instruments IncorporatedInventors: Arvind Kumar, Shobhit Singhal, Vikas Lakhanpal
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Publication number: 20140133613Abstract: Apparatuses and methods for phase aligning at least two clocks used by respective first and second circuitry systems, such as a memory controller and a DDR PHY interface in a system on a chip system. A first circuit samples a phase of a first clock used by the first circuitry system, and then a delay circuit selectively delays a second clock used by the second circuitry system and sets a delayed timing of the second clock. To economize resources and reduce chip area, a logic circuit receives the sampled phase of the first clock, determines which delayed timing matches timing of the sampled phase, and sets the delay circuit to a fixed delayed timing corresponding to the delayed timing that matches the sampled phase. Thus, phase alignment of the two clocks is achieved with fewer resources.Type: ApplicationFiled: November 12, 2012Publication date: May 15, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Arvind Kumar, Shobhit Singhal, Vikas Lakhanpal, Kalpesh Amrutlal Shah