Patents by Inventor Shobhit Sonakiya
Shobhit Sonakiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9690630Abstract: System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.Type: GrantFiled: March 3, 2015Date of Patent: June 27, 2017Assignee: Synopsys, Inc.Inventors: Navendu Sinha, William Charles Jordan, Bryon Irwin Moyer, Stephen John Joseph Fricke, Roberto Attias, Akash Renukadas Deshpande, Vineet Gupta, Shobhit Sonakiya
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Patent number: 9460034Abstract: Structured block transfer module, system architecture, and method for transferring content or data. Circuit allowing content in one memory to be shifted, moved, or copied to another memory with no direction from a host, the circuit comprising: a connection manager, at least one copy engine, and a connection between the connection manager and the copy engine. Method for transferring the contents of one of a number of blocks of source memory to one of a number of possible destination memories comprising: selecting source memory; selecting available destination memory; marking the selected destination as no longer available; copying contents of selected source memory into selected destination memory; and marking selected source as available.Type: GrantFiled: February 28, 2014Date of Patent: October 4, 2016Assignee: Synopsys, Inc.Inventors: Roberto Attias, William Charles Jordan, Bryon Irwin Moyer, Stephen John Joseph Fricke, Akash Renukadas Deshpande, Navendu Sinha, Vineet Gupta, Shobhit Sonakiya
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Patent number: 9430427Abstract: Structured block transfer module, system architecture, and method for transferring content or data. Circuit allowing content in one memory to be shifted, moved, or copied to another memory with no direction from a host., the circuit comprising: a connection manager, at least one copy engine, and a connection between the connection manager and the copy engine. Method for transferring the contents of one of a number of blocks of source memory to one of a number of possible destination memories comprising: selecting source memory; selecting available destination memory; marking the selected destination as no longer available; copying contents of selected source memory into selected destination memory; and marking selected source as available.Type: GrantFiled: March 3, 2014Date of Patent: August 30, 2016Assignee: Synopsys, Inc.Inventors: Roberto Attias, William Charles Jordan, Bryon Irwin Moyer, Stephen John Joseph Fricke, Akash Renukadas Deshpande, Navendu Sinha, Vineet Gupta, Shobhit Sonakiya
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Publication number: 20150178136Abstract: System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.Type: ApplicationFiled: March 3, 2015Publication date: June 25, 2015Inventors: Navendu Sinha, William Charles Jordon, Bryon Irwin Moyer, Stephen John Joseph Fricke, Robert Attias, Akash Renukadas Deshpande, Vineet Gupta, Shobhit Sonakiya
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Patent number: 9003166Abstract: System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.Type: GrantFiled: January 25, 2012Date of Patent: April 7, 2015Assignee: Synopsys, Inc.Inventors: Navendu Sinha, William Charles Jordan, Bryon Irwin Moyer, Stephen John Joseph Fricke, Roberto Attias, Akash Renukadas Deshpande, Vineet Gupta, Shobhit Sonakiya
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Publication number: 20140181343Abstract: Structured block transfer module, system architecture, and method for transferring content or data. Circuit allowing content in one memory to be shifted, moved, or copied to another memory with no direction from a host, the circuit comprising: a connection manager, at least one copy engine, and a connection between the connection manager and the copy engine. Method for transferring the contents of one of a number of blocks of source memory to one of a number of possible destination memories comprising: selecting source memory; selecting available destination memory; marking the selected destination as no longer available; copying contents of selected source memory into selected destination memory; and marking selected source as available.Type: ApplicationFiled: March 3, 2014Publication date: June 26, 2014Applicant: Synopsys, Inc.Inventors: Roberto Attias, William Charles Jordan, Bryon Irwin Moyer, Stephen John Joseph Fricke, Akash Renukadas Deshpande, Navendu Sinha, Vineet Gupta, Shobhit Sonakiya
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Publication number: 20140181447Abstract: Structured block transfer module, system architecture, and method for transferring content or data. Circuit allowing content in one memory to be shifted, moved, or copied to another memory with no direction from a host, the circuit comprising: a connection manager, at least one copy engine, and a connection between the connection manager and the copy engine. Method for transferring the contents of one of a number of blocks of source memory to one of a number of possible destination memories comprising: selecting source memory; selecting available destination memory; marking the selected destination as no longer available; copying contents of selected source memory into selected destination memory; and marking selected source as available.Type: ApplicationFiled: February 28, 2014Publication date: June 26, 2014Applicant: Synopsys, Inc.Inventors: Roberto Attias, William Charles Jordan, Bryon Irwin Moyer, Stephen John Joseph Fricke, Akash Renukadas Deshpande, Navendu Sinha, Vineet Gupta, Shobhit Sonakiya
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Patent number: 8706987Abstract: Structured block transfer module, system architecture, and method for transferring content or data. Circuit allowing content in one memory to be shifted, moved, or copied to another memory with no direction from a host, the circuit comprising: a connection manager, at least one copy engine, and a connection between the connection manager and the copy engine. Method for transferring the contents of one of a number of blocks of source memory to one of a number of possible destination memories comprising: selecting source memory; selecting available destination memory; marking the selected destination as no longer available; copying contents of selected source memory into selected destination memory; and marking selected source as available.Type: GrantFiled: December 1, 2006Date of Patent: April 22, 2014Assignee: Synopsys, Inc.Inventors: Roberto Attias, William Charles Jordan, Bryon Irwin Moyer, Stephen John Joseph Fricke, Akash Renukadas Deshpande, Navendu Sinha, Vineet Gupta, Shobhit Sonakiya
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Patent number: 8458302Abstract: In an example embodiment, a wireless distribution system obtains data for advertised data flows, such as multimedia traffic flows, by snooping attribute details of session description protocol (SDP) announcements. The wireless distribution system can use the data for functions such as admissions control, load balancing, and/or multicast to unicast conversion decisions.Type: GrantFiled: December 20, 2010Date of Patent: June 4, 2013Assignee: Cisco Technology, Inc.Inventors: Tak Ming Pang, Hari Rangarajan, Jianxia Ning, Shobhit Sonakiya
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Patent number: 8289966Abstract: Packet ingress/egress block and logic and system and method for receiving, transmitting, and managing packetized data. System including a line port; a computing resource output port; a host interface; a memory, and a block that: receives information on the line port, creates a context including information for managing computation derived from the received information, and sends context out on computing resource output port. Device comprising first circuit component including line port that receives information, second circuit component that generates context information including an information for managing computation derived from the received unit of information; and third circuit component that communicates the generated context out to a computing resource output port.Type: GrantFiled: December 1, 2006Date of Patent: October 16, 2012Assignee: Synopsys, Inc.Inventors: Stephen John Joseph Fricke, William Charles Jordan, Bryon Irwin Moyer, Roberto Attias, Akash Renukadas Deshpande, Navendu Sinha, Vineet Gupta, Shobhit Sonakiya
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Publication number: 20120158948Abstract: In an example embodiment, a wireless distribution system obtains data for advertised data flows, such as multimedia traffic flows, by snooping attribute details of session description protocol (SDP) announcements. The wireless distribution system can use the data for functions such as admissions control, load balancing, and/or multicast to unicast conversion decisions.Type: ApplicationFiled: December 20, 2010Publication date: June 21, 2012Inventors: Tak Ming PANG, Hari Rangarajan, Jianxia Ning, Shobhit Sonakiya
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Publication number: 20120124588Abstract: System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.Type: ApplicationFiled: January 25, 2012Publication date: May 17, 2012Applicant: SYNOPSYS, INC.Inventors: Navendu Sinha, William Charles Jordan, Bryon Irwin Moyer, Stephen John Joseph Fricke, Roberto Attias, Akash Renukadas Deshpande, Vineet Gupta, Shobhit Sonakiya
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Patent number: 8127113Abstract: System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.Type: GrantFiled: December 1, 2006Date of Patent: February 28, 2012Assignee: Synopsys, Inc.Inventors: Navendu Sinha, William Charles Jordan, Bryon Irwin Moyer, Stephen John Joseph Fricke, Roberto Attias, Akash Renukadas Deshpande, Vineet Gupta, Shobhit Sonakiya