Patents by Inventor Shogo FURUYA
Shogo FURUYA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220173089Abstract: The present invention is a method for producing an electronic device having a drive circuit including a solar cell structure, the method including the steps of: obtaining a bonded wafer by bonding a first wafer having a plurality of independent solar cell structures including a compound semiconductor, the solar cell structures being formed on a starting substrate by epitaxial growth, and a second wafer having a plurality of independent drive circuits formed, so that the plurality of solar cell structures and the plurality of drive circuits are respectively superimposed; wiring the bonded wafer so that electric power can be supplied from the plurality of solar cell structures to the plurality of drive circuits respectively; and producing an electronic device having the drive circuit including the solar cell structure by dicing the bonded wafer. This provides a method for producing an electronic device including a drive circuit and a solar cell structure in one chip and having a suppressed production cost.Type: ApplicationFiled: March 16, 2020Publication date: June 2, 2022Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Junya ISHIZAKI, Shogo FURUYA, Tomohiro AKIYAMA
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Publication number: 20220013557Abstract: There is provided a solid-state imaging device having a configuration suitable for high integration. The solid-state imaging device includes a semiconductor layer, a photoelectric converter, a storage capacitor, and a first transistor. The photoelectric converter is provided in the semiconductor layer, and generates an electric charge corresponding to a received light amount by photoelectric conversion. The storage capacitor is provided on the semiconductor layer, and includes a first insulating film having a first electrical film thickness. The first transistor is provided on the semiconductor layer, and includes a second insulating film having a second electrical film thickness larger than the first electrical film thickness.Type: ApplicationFiled: November 19, 2019Publication date: January 13, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Shogo FURUYA, Yorito SAKANO, Ryo TAKAHASHI, Atsushi SUZUKI, Ryoichi YOSHIKAWA, Jun SUENAGA, Shinichi KOGA, Yohei CHIBA, Tadamasa SHIOYAMA
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Patent number: 10917591Abstract: The present disclosure relates to a solid-state imaging device and a method of controlling a solid-state imaging device, and an electronic device for enabling appropriate expansion of a dynamic range with respect to an object moving at a high speed or an object having a large luminance difference between bright and dark to reduce motion distortion (motion artifact). Exposure of a plurality of pixels is individually controlled in units of pixels. The present disclosure can be applied to a solid-state imaging device.Type: GrantFiled: March 30, 2018Date of Patent: February 9, 2021Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Satoko Iida, Masaki Sakakibara, Yorito Sakano, Naosuke Asari, Masaaki Takizawa, Tomohiko Asatsuma, Shogo Furuya
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Publication number: 20200029036Abstract: The present disclosure relates to a solid-state imaging device and a method of controlling a solid-state imaging device, and an electronic device for enabling appropriate expansion of a dynamic range with respect to an object moving at a high speed or an object having a large luminance difference between bright and dark to reduce motion distortion (motion artifact). Exposure of a plurality of pixels is individually controlled in units of pixels. The present disclosure can be applied to a solid-state imaging device.Type: ApplicationFiled: March 30, 2018Publication date: January 23, 2020Inventors: SATOKO IIDA, MASAKI SAKAKIBARA, YORITO SAKANO, NAOSUKE ASARI, MASAAKI TAKIZAWA, TOMOHIKO ASATSUMA, SHOGO FURUYA
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Patent number: 10388831Abstract: A light-emitting device including a window layer-cum-support substrate, a light-emitting portion provided on the window layer-cum-support substrate and including a second semiconductor layer of a second conductivity type, an active layer, and first semiconductor layer of a first conductivity type in stated order, a first ohmic electrode provided on the first semiconductor layer, and insulator top coat at least partially coating the first semiconductor layer surface and light-emitting portion side surface, wherein the first semiconductor layer surface and surface of the window layer-cum-support substrate are roughened, and the first semiconductor layer includes at least two layers of an active-layer-side layer and roughened-side layer, and roughened-side layer is formed of material having lower Al content than the active-layer-side layer.Type: GrantFiled: December 9, 2015Date of Patent: August 20, 2019Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Junya Ishizaki, Shogo Furuya
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Publication number: 20170352783Abstract: A light-emitting device including a window layer-cum-support substrate, a light-emitting portion provided on the window layer-cum-support substrate and including a second semiconductor layer of a second conductivity type, an active layer, and first semiconductor layer of a first conductivity type in stated order, a first ohmic electrode provided on the first semiconductor layer, and insulator top coat at least partially coating the first semiconductor layer surface and light-emitting portion side surface, wherein the first semiconductor layer surface and surface of the window layer-cum-support substrate are roughened, and the first semiconductor layer includes at least two layers of an active-layer-side layer and roughened-side layer, and roughened-side layer is formed of material having lower Al content than the active-layer-side layer.Type: ApplicationFiled: December 9, 2015Publication date: December 7, 2017Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Junya ISHIZAKI, Shogo FURUYA
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Patent number: 8916917Abstract: According to one embodiment, a solid-state imaging device includes a first element formation region surrounded by an element isolation region in a semiconductor substrate having a first and a second surface, an upper element isolation layer on the first surface in the element formation region, a lower element isolation layer between the second surface and the upper element isolation layer, a first photodiode in the element formation region, a floating diffusion in the element formation region, and a first transistor disposed between the first photodiode and the floating diffusion. A side surface of the lower element isolation layer protrudes closer to the transistor than a side surface of the upper element isolation layer.Type: GrantFiled: February 3, 2012Date of Patent: December 23, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Shogo Furuya, Hirofumi Yamashita, Tetsuya Yamaguchi
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Patent number: 8878265Abstract: According to one embodiment, a solid-state imaging device includes a first element formation region surrounded by an element isolation region in a semiconductor substrate having a first and a second surface, an upper element isolation layer on the first surface in the element formation region, a lower element isolation layer between the second surface and the upper element isolation layer, a first photodiode in the element formation region, a floating diffusion in the element formation region, and a first transistor disposed between the first photodiode and the floating diffusion. A side surface of the lower element isolation layer protrudes closer to the transistor than a side surface of the upper element isolation layer.Type: GrantFiled: February 3, 2012Date of Patent: November 4, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Shogo Furuya, Hirofumi Yamashita, Tetsuya Yamaguchi
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Publication number: 20120199894Abstract: According to one embodiment, a solid-state imaging device includes a first element formation region surrounded by an element isolation region in a semiconductor substrate having a first and a second surface, an upper element isolation layer on the first surface in the element formation region, a lower element isolation layer between the second surface and the upper element isolation layer, a first photodiode in the element formation region, a floating diffusion in the element formation region, and a first transistor disposed between the first photodiode and the floating diffusion. A side surface of the lower element isolation layer protrudes closer to the transistor than a side surface of the upper element isolation layer.Type: ApplicationFiled: February 3, 2012Publication date: August 9, 2012Inventors: Shogo FURUYA, Hirofumi Yamashita, Tetsuya Yamaguchi
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Publication number: 20110042552Abstract: According to one embodiment, a solid-state imaging device with an array arrangement of unit pixels including photoelectric conversion parts configured to generate signal charges by photoelectric conversion and a signal scanning circuit part, the signal scanning circuit part being provided on a second semiconductor layer different from a first semiconductor layer including the photoelectric conversion parts, the second semiconductor layer being stacked above the front side of the first semiconductor layer via an insulating film, and the first semiconductor layer being so configured that a pixel separation insulating film is buried in pixel boundary parts and read transistors configured to read signal charges generated by the photoelectric conversion parts are formed at the front side of the first semiconductor layer.Type: ApplicationFiled: August 9, 2010Publication date: February 24, 2011Inventors: Shogo FURUYA, Hirofumi Yamashita, Yusuke Kohyama