Abstract: An operational amplifier includes a first amplifier to which an input signal is applied, and a second amplifier to which an output of the first amplifier is applied, wherein the second amplifier includes a first transistor including a gate to which the output of the first amplifier is applied, and a second transistor including a gate to which the output of the first amplifier is applied, and a drain coupled to a source of the first transistor.

Abstract: An operational amplifier includes a first amplifier to which an input signal is applied, and a second amplifier to which an output of the first amplifier is applied, wherein the second amplifier includes a first transistor including a gate to which the output of the first amplifier is applied, and a second transistor including a gate to which the output of the first amplifier is applied, and a drain coupled to a source of the first transistor.

Abstract: A digital-analog converter including a first selection circuit of switch elements, which are coupled to each other and to a high potential power supply, and a second selection circuit of switch elements, which are coupled to each other and to a low potential power supply. First and second voltage dividing circuit each include series-connected resistor elements, each coupled between adjacent switch elements of the corresponding selection circuit. A control circuit provides a control signal to the selection circuits to activate one of the switch elements in each selection circuit and couple the activated switch element to the corresponding potential power supply. The first and second voltage dividing circuits divide voltages of the high and low potential power supplies with the resistor elements between the activated switch elements.

Abstract: A digital-analog converter including a first selection circuit of switch elements, which are coupled to each other and to a high potential power supply, and a second selection circuit of switch elements, which are coupled to each other and to a low potential power supply. First and second voltage dividing circuit each include series-connected resistor elements, each coupled between adjacent switch elements of the corresponding selection circuit. A control circuit provides a control signal to the selection circuits to activate one of the switch elements in each selection circuit and couple the activated switch element to the corresponding potential power supply. The first and second voltage dividing circuits divide voltages of the high and low potential power supplies with the resistor elements between the activated switch elements.

Abstract: It is intended to provide an A/D converter circuit with which, by using a clock signal, on the basis of an analog voltage inputted a predetermined time past, it is possible to select suitably comparators to be operated and comparators to be rested, and which has small consumed power. A parallel-type A/D-converter circuit 200 converts an analog voltage VIN to a digital value DOUT at intervals of a predetermined period by means of a clock signal CLK using chopper-type comparators 1–7. The comparators 1–7 can each be set by first and second setting signals CONT1A etc. to either of an operating state and a resting state. A comparator control circuit section 211 performs logical processing on the comparator outputs OUT1–OUT7 in the preceding conversion to generate the first and second setting signals CONT1A etc., and brings some of the comparators to the operating state and holds the remaining comparators in the resting state.

Abstract: It is intended to provide an A/D converter circuit with which, by using a clock signal, on the basis of an analog voltage inputted a predetermined time past, it is possible to select suitably comparators to be operated and comparators to be rested, and which has small consumed power. A parallel-type A/D-converter circuit 200 converts an analog voltage VIN to a digital value DOUT at intervals of a predetermined period by means of a clock signal CLK using chopper-type comparators 1-7. The comparators 1-7 can each be set by first and second setting signals CONT1A etc. to either of an operating state and a resting state. A comparator control circuit section 211 performs logical processing on the comparator outputs OUT1-OUT7 in the preceding conversion to generate the first and second setting signals CONTLA etc., and brings some of the comparators to the operating state and holds the remaining comparators in the resting state.

Abstract: It is intended to provide an A/D converter circuit with which, by using a clock signal, on the basis of an analog voltage inputted a predetermined time past, it is possible to select suitably comparators to be operated and comparators to be rested, and which has small consumed power. A parallel-type A/D-converter circuit 200 converts an analog voltage VIN to a digital value DOUT at intervals of a predetermined period by means of a clock signal CLK using chopper-type comparators 1-7. The comparators 1-7 can each be set by first and second setting signals CONT1A etc. to either of an operating state and a resting state. A comparator control circuit section 211 performs logical processing on the comparator outputs OUT1-OUT7 in the preceding conversion to generate the first and second setting signals CONT1A etc., and brings some of the comparators to the operating state and holds the remaining comparators in the resting state.

Abstract: It is intended to provide an A/D converter circuit with which, by using a clock signal, on the basis of an analog voltage inputted a predetermined time past, it is possible to select suitably comparators to be operated and comparators to be rested, and which has small consumed power. A parallel-type A/D-converter circuit 200 converts an analog voltage VIN to a digital value DOUT at intervals of a predetermined period by means of a clock signal CLK using chopper-type comparators 1-7. The comparators 1-7 can each be set by first and second setting signals CONT1A etc. to either of an operating state and a resting state. A comparator control circuit section 211 performs logical processing on the comparator outputs OUT1-OUT7 in the preceding conversion to generate the first and second setting signals CONT1A etc., and brings some of the comparators to the operating state and holds the remaining comparators in the resting state.

Abstract: A water-dispersible blocked isocyanate composition, including an isocyanate group-terminated precursor and a blocking agent for blocking a free isocyanate group of the precursor, wherein the precursor includes at least an organic diisocyanate, a low-molecular glycol, and a hydrophilic surfactant having at least one active hydrogen group. The precursor also has an isocyanurate ring structure; an average functional group number (f) satisfying 2.0.ltoreq.f.ltoreq.4.2; a low-molecular glycol content (X) satisfying 0.5 wt. %.ltoreq..times..ltoreq.15 wt. %; and a hydrophilic surfactant content(Y) satisfying 0.1 wt. %.ltoreq.Y.ltoreq.50 wt. %.

Abstract: A water-dispersible blocked isocyanate composition, including an isocyanate group-terminated precursor and a blocking agent for blocking a free isocyanate group of the precursor, wherein the precursor includes at least an organic diisocyanate, a low-molecular glycol, and a hydrophilic surfactant having at least one active hydrogen group. The precursor also has an isocyanurate ring structure; an average functional group number (f) satisfying 2.0.ltoreq.f.ltoreq.4.2; a low-molecular glycol content (X) satisfying 0.5 wt. %.ltoreq.X .ltoreq.15 wt. %; and a hydrophilic surfactant content(Y) satisfying 0.1 wt. % .ltoreq.Y.ltoreq.50 wt. %.