Patents by Inventor Shogo Matsuo

Shogo Matsuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240355693
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor element on a substrate. A first surface of the semiconductor element faces away from the substrate and a second surface faces the substrate. A first surface electrode is on the first surface of the semiconductor element. A bonding wire is connected to the first surface electrode at a bonding portion. A first sealing member covers the bonding portion. A second sealing member covers a portion of the first surface electrode outside the bonding portion. A third sealing member covers the first sealing member and the second sealing member.
    Type: Application
    Filed: April 9, 2024
    Publication date: October 24, 2024
    Inventors: Shogo MINAMI, Tomohiro IGUCHI, Katsuya SATO, Keiichiro MATSUO
  • Publication number: 20240312947
    Abstract: A semiconductor device according to an embodiment includes: an insulating substrate having a first metal layer and a second metal layer; a semiconductor chip on the first metal layer having an upper electrode and a lower electrode connected to the first metal layer; a bonding wire having a first end portion connected to the upper electrode and a second end portion connected to the second metal layer; a first resin layer covering the semiconductor chip and the bonding wire, the first resin layer containing a first resin; a second resin layer covering a bonding portion between the first end portion and the upper electrode containing a second resin having a Young's modulus higher than that of the first resin; a third resin layer on the first resin layer, the third resin layer containing a third resin having a moisture permeability lower than that of the first resin.
    Type: Application
    Filed: August 3, 2023
    Publication date: September 19, 2024
    Inventors: Tomohiro IGUCHI, Tatsuya HIRAKAWA, Shogo MINAMI, Hiroyuki MATSUO, Izuru KOMATSU
  • Publication number: 20240215148
    Abstract: A connector includes: a circuit board; a first heat transfer material arranged on a principal surface of the circuit board; a first shell having an end mated with a mating connector in a state in which the terminal end portion of the circuit board protrudes from the end, and includes an opposite opposed to at least a part of a target region which is a region other than the terminal end portion, covers at least a part of the target region, and is conductive; a second shell connected to an end of the first shell, covers at least a part of the target region of the principal surface, and is thermally conductably connected to the circuit board in contact with the first heat transfer material; and a third shell engaged with the second shell, covers at least a part of the target region of a principal surface, and is conductive.
    Type: Application
    Filed: March 6, 2024
    Publication date: June 27, 2024
    Inventors: Yoichi HASHIMOTO, Sho SUZUKI, Shogo MATSUO
  • Patent number: 11956886
    Abstract: A connector includes: a circuit board; a first heat transfer material arranged on a principal surface of the circuit board; a first shell having an end mated with a mating connector in a state in which the terminal end portion of the circuit board protrudes from the end, and includes an opposite opposed to at least a part of a target region which is a region other than the terminal end portion, covers at least a part of the target region, and is conductive; a second shell connected to an end of the first shell, covers at least a part of the target region of the principal surface, and is thermally conductably connected to the circuit board in contact with the first heat transfer material; and a third shell engaged with the second shell, covers at least a part of the target region of a principal surface, and is conductive.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: April 9, 2024
    Assignee: I-PEX Inc.
    Inventors: Yoichi Hashimoto, Sho Suzuki, Shogo Matsuo
  • Publication number: 20230180440
    Abstract: A connector system (1) includes a connector (10) that detachably mates with a mating connector (20) mounted on an external circuit board (30), and an abutting member (40) fixed to the external circuit board (30). The connector (10) includes a circuit board (200) that connects to an external device via a signal line (300); an electrically conductive first shell (110) through which a terminal portion (201) of the circuit board (200) is inserted and that is electrically connected to the external circuit board (30) via the mating connector (20); and an electrically conductive second shell (120) that covers at least a portion of a target region that is a region, of one main surface (205) of the circuit board (200), other than the terminal portion (201). The abutting member (40) presses at least a portion of the connector (10) toward the external circuit board (30).
    Type: Application
    Filed: April 27, 2021
    Publication date: June 8, 2023
    Applicant: I-PEX Inc.
    Inventors: Shogo MATSUO, Kohei NISHIYAMA, Masashi NAKAMURA
  • Patent number: 11577403
    Abstract: A position correction device according to an embodiment includes a movable part and a pressing part. The movable part is capable of moving a holding part that holds a connection object back and forth in each of a second direction that is orthogonal to a first direction where the holding part is moved therein in order to connect the connection object to a target connector, and a rotational direction where the holding part is rotated therein around an axis along a third direction that is orthogonal to each of the first direction and the second direction as a center. The pressing part presses the movable part that moves in the second direction to move the movable part to a neutral position in the second direction and presses the movable part that moves in the rotational direction to move the movable part to a neutral position in the rotational direction.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: February 14, 2023
    Assignee: DAI-ICHI SEIKO CO., LTD.
    Inventor: Shogo Matsuo
  • Publication number: 20220167493
    Abstract: A connector includes: a circuit board; a first heat transfer material arranged on a principal surface of the circuit board; a first shell having an end mated with a mating connector in a state in which the terminal end portion of the circuit board protrudes from the end, and includes an opposite opposed to at least a part of a target region which is a region other than the terminal end portion, covers at least a part of the target region, and is conductive; a second shell connected to an end of the first shell, covers at least a part of the target region of the principal surface, and is thermally conductably connected to the circuit board in contact with the first heat transfer material; and a third shell engaged with the second shell, covers at least a part of the target region of a principal surface, and is conductive.
    Type: Application
    Filed: April 3, 2020
    Publication date: May 26, 2022
    Applicant: I-PEX Inc.
    Inventors: Yoichi Hashimoto, Sho Suzuki, Shogo Matsuo
  • Publication number: 20190329424
    Abstract: A position correction device according to an embodiment includes a movable part and a pressing part. The movable part is capable of moving a holding part that holds a connection object back and forth in each of a second direction that is orthogonal to a first direction where the holding part is moved therein in order to connect the connection object to a target connector, and a rotational direction where the holding part is rotated therein around an axis along a third direction that is orthogonal to each of the first direction and the second direction as a center. The pressing part presses the movable part that moves in the second direction to move the movable part to a neutral position in the second direction and presses the movable part that moves in the rotational direction to move the movable part to a neutral position in the rotational direction.
    Type: Application
    Filed: April 22, 2019
    Publication date: October 31, 2019
    Applicant: DAI-ICHI SEIKO CO., LTD.
    Inventor: Shogo MATSUO
  • Publication number: 20150372049
    Abstract: A method of manufacturing a semiconductor device includes forming a first film on a semiconductor substrate. The semiconductor substrate includes metal impurities, which may cause defects in the semiconductor device. A second film is formed on the first film such that the first film is between the second film and the semiconductor substrate. The first film, the second film, and the semiconductor substrate are heated. During the heating, which may occur during various manufacturing steps of the semiconductor device, the metal impurities from the semiconductor substrate diffuse into the second film. After the heating, the first and second films are removed from the semiconductor substrate.
    Type: Application
    Filed: February 18, 2015
    Publication date: December 24, 2015
    Inventors: Hideo TAKEYAMA, Masato FUKUMOTO, Shogo MATSUO
  • Patent number: 8329553
    Abstract: A method for manufacturing semiconductor device has forming a plurality of trenches having at least two kinds of aspect ratios on a semiconductor substrate, filling the plurality of trenches with a coating material containing silicon, forming a mask on the coating material in a part of the trenches among the plurality of trenches filled with the coating material, implanting an ion for accelerating oxidation of the coating material into the coating material in the trenches on which the mask is not formed, forming a first insulating film by oxidizing the coating materials into which the ion is implanted, removing the coating material from the part of the trenches after removing the mask and forming a second insulating film in the part of the trenches from which the coating material is removed.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: December 11, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shogo Matsuo, Takeshi Hoshi, Keisuke Nakazawa, Kazuaki Iwasawa
  • Patent number: 8193056
    Abstract: According to one embodiment, a method of fabricating a semiconductor device is disclosed. The method includes the steps of: forming a tunnel insulating film on a semiconductor substrate; forming a floating gate electrode on the tunnel insulating film; and forming a silicon nitride film including a low-density silicon nitride film and a high-density silicon nitride film on the floating gate electrode. The method also includes the steps of: forming an isolation trench thereby to expose the low-density silicon nitride film exposed at least in a portion of a side surface of the isolation trench; forming an isolating insulating film covering an internal surface of the isolation trench; removing the silicon nitride film; and forming an interelectrode insulating film and a control gate electrode both covering the floating gate electrode and the isolating insulating film.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: June 5, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuaki Iwasawa, Shogo Matsuo, Kenichiro Toratani
  • Publication number: 20120034754
    Abstract: A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.
    Type: Application
    Filed: October 13, 2011
    Publication date: February 9, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuaki Iwasawa, Takeshi Hoshi, Keisuke Nakazawa, Shogo Matsuo, Takashi Nakao, Ryu Kato, Tetsuya Kai, Katsuyuki Sekine
  • Patent number: 8080463
    Abstract: A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: December 20, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuaki Iwasawa, Takeshi Hoshi, Keisuke Nakazawa, Shogo Matsuo, Takashi Nakao, Ryu Kato, Tetsuya Kai, Katsuyuki Sekine
  • Publication number: 20110065271
    Abstract: According to one embodiment, a method of fabricating a semiconductor device is disclosed. The method includes the steps of: forming a tunnel insulating film on a semiconductor substrate; forming a floating gate electrode on the tunnel insulating film; and forming a silicon nitride film including a low-density silicon nitride film and a high-density silicon nitride film on the floating gate electrode. The method also includes the steps of: forming an isolation trench thereby to expose the low-density silicon nitride film exposed at least in a portion of a side surface of the isolation trench; forming an isolating insulating film covering an internal surface of the isolation trench; removing the silicon nitride film; and forming an interelectrode insulating film and a control gate electrode both covering the floating gate electrode and the isolating insulating film.
    Type: Application
    Filed: September 9, 2010
    Publication date: March 17, 2011
    Inventors: Kazuaki IWASAWA, Shogo MATSUO, Kenichiro TORATANI
  • Publication number: 20100311220
    Abstract: A method for manufacturing semiconductor device has forming a plurality of trenches having at least two kinds of aspect ratios on a semiconductor substrate, filling the plurality of trenches with a coating material containing silicon, forming a mask on the coating material in a part of the trenches among the plurality of trenches filled with the coating material, implanting an ion for accelerating oxidation of the coating material into the coating material in the trenches on which the mask is not formed, forming a first insulating film by oxidizing the coating materials into which the ion is implanted, removing the coating material from the part of the trenches after removing the mask and forming a second insulating film in the part of the trenches from which the coating material is removed.
    Type: Application
    Filed: March 23, 2010
    Publication date: December 9, 2010
    Inventors: Shogo MATSUO, Takeshi Hoshi, Keisuke Nakazawa, Kazuaki Iwasawa
  • Publication number: 20100190317
    Abstract: A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.
    Type: Application
    Filed: January 21, 2010
    Publication date: July 29, 2010
    Inventors: Kazuaki IWASAWA, Takeshi Hoshi, Keisuke Nakazawa, Shogo Matsuo, Takashi Nakao, Ryu Kato, Tetsuya Kai, Katsuyuki Sekine
  • Patent number: 5818094
    Abstract: A semiconductor element-housing package which hermetically houses a semiconductor element for protection against moisture in the atmosphere by bonding an insulating substrate and a lid by means of a sealing material, with a moisture absorbent having surface pores 10-100 .ANG. in radius which is mixed in the insulating substrate and/or the sealing material formed of a resin.
    Type: Grant
    Filed: May 23, 1996
    Date of Patent: October 6, 1998
    Assignee: Kyocera Corporation
    Inventor: Shogo Matsuo