Abstract: A reconfigurable circuit (10) according to the present invention includes: a switching element group that is formed by a plurality of switching elements (1), an ON state and an OFF state of the switching element being rewritable in accordance with a resistive state; and a configuration controller (60) that senses the resistive state of each of the switching elements and programs each switching element, wherein the configuration controller (60) senses the resistive state of each switching element (1) by applying an inspection-purpose voltage across the opposite electrodes of the switching element (1), and when the sensed resistive state is abnormal, the configuration controller applies a programming voltage across the opposite electrodes of the switching element such that the resistive state of the switching element becomes the programmed resistive state.

Abstract: A power converter includes a plurality of converters, a control device, and a signal adjustment device. The converters are connected to the photoelectric conversion cells respectively. The control device generates a base signal based on electrical power output from at least one type of photoelectric conversion cell out of plurality types of photoelectric conversion cells. The base signal is a signal that is a base for a plurality of control signals to control the converters individually so that electrical power output from the photoelectric conversion cells reaches a maximum power point of each of the photoelectric conversion cells. The signal adjustment device multiplies the base signal by a constant, and supplies a signal generated by the multiplication by the constant, as the control signal, to the converter which is a signal supply destination.

Abstract: Bidirectional buffer 20D includes: multiplexer 30 that is equipped with rewriteable variable-resistance nonvolatile switch elements for each input terminal; tristate buffer 51 that is equipped with rewriteable variable-resistance nonvolatile switch elements for each output terminal and that receives the output of multiplexer 30 as input; demultiplexer 31 that receives the output of tristate buffer 51 as input; programming transistor tr0 whose drain terminal is connected to the input terminal of tristate buffer 51; and programming transistor tr1 whose drain terminal is connected to the output terminal of tristate buffer 51. Input terminals i1 and i3 of multiplexer 30 are connected to respective output terminals t1 and t2 of demultiplexer 31.

Abstract: A radio tag sensor system includes a plurality of radio tag sensor chips, which incorporate respective sensors, store unique identification numbers, a plurality of micro base stations, and a central processing unit which perform communications with the micro base stations via a connection network. Each of the micro base stations performs wireless communications with and wirelessly supplies electric power to only those of the radio tag sensor chips which are disposed in an assigned region thereof. Each of the assigned regions includes at least one radio tag sensor chip which is not included in the other assigned regions. The central processing unit controls the communications via the connection network. The central processing unit collects the sensed values from sensors of the radio tag sensor chips through the micro base stations, generates a spatial distribution map of the sensed values, and updates the spatial distribution map with time.

Abstract: Bidirectional buffer 20D includes: multiplexer 30 that is equipped with rewriteable variable-resistance nonvolatile switch elements for each input terminal; tristate buffer 51 that is equipped with rewriteable variable-resistance nonvolatile switch elements for each output terminal and that receives the output of multiplexer 30 as input; demultiplexer 31 that receives the output of tristate buffer 51 as input; programming transistor tr0 whose drain terminal is connected to the input terminal of tristate buffer 51; and programming transistor tr1 whose drain terminal is connected to the output terminal of tristate buffer 51. Input terminals i1 and i3 of multiplexer 30 are connected to respective output terminals t1 and t2 of demultiplexer 31.

Abstract: A reconfigurable circuit of the present invention is characterized in being provided with: a first programmable wiring group, which is disposed in the first direction; a second programmable wiring group, which is disposed in the second direction that intersects the first direction; a first switch element array, which connects the programmable wiring groups to each other at the intersecting points of the first programmable wiring group and the branch line group of a functional block input wiring group or at the intersecting points of the branch line group of the first programmable wiring group and the functional block input wiring group; a second switch element array, which connects the programmable wiring groups to each other at the intersecting points of the first programmable wiring group and functional block output wiring; and a third switch element array, which connects the programmable wiring groups to each other at the intersecting points of the second programmable wiring group and the first programmabl

Abstract: A reconfigurable device test scheme is provided for making a test of a reconfigurable device with configuration data which is loaded a smaller number of times. A reconfigurable device used herein holds a plurality of configuration data and is capable of instantaneously switching which configuration is implemented thereby. Specifically, one transfer configuration data and one or more test configuration data are previously loaded in a configuration memory of the reconfigurable device, and a test is made while sequentially switching the transfer configuration data and the test configuration data. In this way, the same configuration data need not be reloaded over and over, so that the test can be made with a smaller number of times of loading as compared with before.

Abstract: A reconfigurable circuit generation device comprises: a netlist generation unit that generates as a shared netlist a netlist that can be shared among a plurality of netlists having a common portion, and a resource reduction unit that reduces resources of the reconfigurable circuit where the plurality of netlists are to be implemented, in a range in which the shared netlist can be implemented.

Abstract: A circuit design system 10 includes storage means 11 to store structure description information 11a of a reconfigurable circuit including an array of cells 1 including a plurality of switches 2, and application circuit netlist information 11b used to specify an application, circuit generation unit 12a to generate structure description information 11a based on the structure description information 11a and the application circuit netlist information 11b stored in the storage means 11, and circuit evaluation unit 12b to evaluate the structure description information 11a generated by the circuit generation unit 12a, wherein the circuit generation unit 12a generates the structure description information 11a by deleting at least one of the switches 2 from the structure description information 11a based on an evaluation result obtained by the circuit evaluation unit 12b.

Abstract: A reconfigurable circuit (10) according to the present invention includes: a switching element group that is formed by a plurality of switching elements (1), an ON state and an OFF state of the switching element being rewritable in accordance with a resistive state; and a configuration controller (60) that senses the resistive state of each of the switching elements and programs each switching element, wherein the configuration controller (60) senses the resistive state of each switching element (1) by applying an inspection-purpose voltage across the opposite electrodes of the switching element (1), and when the sensed resistive state is abnormal, the configuration controller applies a programming voltage across the opposite electrodes of the switching element such that the resistive state of the switching element becomes the programmed resistive state.

Abstract: A reconfigurable circuit of the present invention is characterized in being provided with: a first programmable wiring group, which is disposed in the first direction; a second programmable wiring group, which is disposed in the second direction that intersects the first direction; a first switch element array, which connects the programmable wiring groups to each other at the intersecting points of the first programmable wiring group and the branch line group of a functional block input wiring group or at the intersecting points of the branch line group of the first programmable wiring group and the functional block input wiring group; a second switch element array, which connects the programmable wiring groups to each other at the intersecting points of the first programmable wiring group and functional block output wiring; and a third switch element array, which connects the programmable wiring groups to each other at the intersecting points of the second programmable wiring group and the first programmabl

Abstract: Provided is a reconfigurable logic circuit that can effectively use a preposition logic that composes a logic block. The reconfigurable logic block according to the present invention includes a plurality of logic blocks (199) having a full adder (30), two preposition logics (20) that perform a plurality of logic operations according to configuration data, an extended logic block (60) that can perform the logic operation of one or more kinds. Outputs (21A and 21B) of the preposition logic are respectively connected to two argument inputs (A and B) of the full adder (30). A carry output (CO) of the full adder (30) is connected to the extended logic block (60). One selected from a plurality of signals including a fixed logic value is input to a carry input (CI) of the full adder according to the configuration data, and the extended logic block of other logic block generates an output signal according to an output of the extended logic block.

Abstract: A radio tag sensor system includes a plurality of radio tag sensor chips, which incorporate respective sensors, store unique identification numbers, a plurality of micro base stations, and a central processing unit which perform communications with the micro base stations via a connection network. Each of the micro base stations performs wireless communications with and wirelessly supplies electric power to only those of the radio tag sensor chips which are disposed in an assigned region thereof. Each of the assigned regions includes at least one radio tag sensor chip which is not included in the other assigned regions. The central processing unit controls the communications via the connection network. The central processing unit collects the sensed values from sensors of the radio tag sensor chips through the micro base stations, generates a spatial distribution map of the sensed values, and updates the spatial distribution map with time.

Abstract: A solar power generation apparatus in which a solar cell unit is disposed at focal position in an optical system, which includes a single optical system and formulated so as to collect and spectrally separate incident light that falls in parallel to an optical axis, and focus each of the spectrally separated wavelength band lights at a different focal position on the optical axis. The solar cell unit includes a plurality of solar cells, each including, a junction unit disposed on a circumference of a substrate portion disposed along the optical axis, a surface of the junction portion forming a light receiving surface with a different sensitive wavelength band. The plurality of solar cells are arrayed along the optical axis, and each of the solar cells is disposed at one of the focal positions at which the wavelength band light corresponding to each the different sensitive wavelength band is focused.

Abstract: A plurality of three-terminal variable resistance switching elements each having a source electrode, a drain electrode, and a gate electrode are connected to each other in series. The source electrode of each of the three-terminal variable resistance switching elements and the drain electrode of its adjacent three-terminal variable resistance switching element are connected to each other through a wiring segment to form a lane. A potential holding section for holding a predetermined potential level is connected to the wiring segment. A column group is configured by selecting one of the three-terminal variable resistance elements in each lane. A common gate line is connected to each of the gate electrodes of the three-terminal variable resistance elements belonging to the column group.

Abstract: Provided is a reconfigurable logic circuit that can effectively use a preposition logic that composes a logic block. The reconfigurable logic block according to the present invention includes a plurality of logic blocks (199) having a full adder (30), two preposition logics (20) that perform a plurality of logic operations according to configuration data, an extended logic block (60) that can perform the logic operation of one or more kinds. Outputs (21A and 21B) of the preposition logic are respectively connected to two argument inputs (A and B) of the full adder (30). A carry output (CO) of the full adder (30) is connected to the extended logic block (60). One selected from a plurality of signals including a fixed logic value is input to a carry input (CI) of the full adder according to the configuration data, and the extended logic block of other logic block generates an output signal according to an output of the extended logic block.

Abstract: A reconfigurable circuit generation device comprises: a netlist generation unit that generates as a shared netlist a netlist that can be shared among a plurality of netlists having a common portion, and a resource reduction unit that reduces resources of the reconfigurable circuit where the plurality of netlists are to be implemented, in a range in which the shared netlist can be implemented.

Abstract: A configurable circuit of the present invention includes a plurality of logic blocks (4), and a programmable bus which can program connections of plurality of logic blocks (4). The programmable bus includes a plurality of wires (11—x) arranged for each of signal transmission ranges corresponding to plurality of logic blocks (4), direct wire connection switch (711—x) which can program whether to directly connect or disconnect the wires between the adjacent signal transmission ranges, input selector (30—x) which can program a connection with any one of the plurality of wires, and programmable switch (40—x) which can program whether to make a connection with the wire corresponding to the adjacent signal transmission range for each of the plurality of wires. A plurality of programmable switches (40—x) are arranged for at least one of plurality of logic blocks (4).

Abstract: A circuit design system 10 includes storage means 11 to store structure description information 11a of a reconfigurable circuit including an array of cells 1 including a plurality of switches 2, and application circuit netlist information 11b used to specify an application, circuit generation unit 12a to generate structure description information 11a based on the structure description information 11a and the application circuit netlist information 11b stored in the storage means 11, and circuit evaluation unit 12b to evaluate the structure description information 11a generated by the circuit generation unit 12a, wherein the circuit generation unit 12a generates the structure description information 11a by deleting at least one of the switches 2 from the structure description information 11a based on an evaluation result obtained by the circuit evaluation unit 12b.

Abstract: A configurable circuit of the present invention includes a plurality of logic blocks (4), and a programmable bus which can program connections of plurality of logic blocks (4). The programmable bus includes a plurality of wires (11_x) arranged for each of signal transmission ranges corresponding to plurality of logic blocks (4), direct wire connection switch (711_x) which can program whether to directly connect or disconnect the wires between the adjacent signal transmission ranges, input selector (30_x) which can program a connection with any one of the plurality of wires, and programmable switch (40_x) which can program whether to make a connection with the wire corresponding to the adjacent signal transmission range for each of the plurality of wires. A plurality of programmable switches (40_x) are arranged for at least one of plurality of logic blocks (4).