Patents by Inventor Shogo Shibazaki
Shogo Shibazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8503259Abstract: A memory test is performed by sequentially generating a number of n-bit addresses, whose first to k-th bits (1?k?n) are all set to one of two values, 0 or 1, and whose (k+1)th to n-th bits are all set to the other one of the two values, for all k's which range from 1 to n; writing first test data to each of the generated addresses in the memory; reading second test data from each of the addresses in the memory; and comparing the first test data with the second test data.Type: GrantFiled: March 17, 2009Date of Patent: August 6, 2013Assignee: Fujitsu LimitedInventors: Shogo Shibazaki, Shinkichi Gama, Hideyuki Negi, Takeshi Nagase, Chikahiro Deguchi, Yutaka Sekino
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Patent number: 8143901Abstract: A test apparatus includes an up counter, a down counter, a selector that selects either an up counter output from the up counter or a down counter output from the down counter, an inversion circuit that inverts either the counter output selected by the selector or the counter output nonselected by the selector, and a comparison circuit that compares the counter output inverted by the inversion circuit and the other counter output.Type: GrantFiled: February 19, 2009Date of Patent: March 27, 2012Assignee: Fujitsu LimitedInventors: Chikahiro Deguchi, Yutaka Sekino, Shogo Shibazaki, Shinkichi Gama, Takeshi Nagase, Hideyuki Negi
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Patent number: 7689836Abstract: An encryption/decryption processing unit performs encryption/decryption processing of data transmitted from a host system, and encryption/decryption processing of key data used for encryption/decryption of the data. A key data buffer temporarily stores encrypted key data. A key data buffer temporarily stores unencrypted key data. An external memory interface controls flash memory attached outside, and reads/writes encrypted key data stored in the key data buffer.Type: GrantFiled: December 21, 2005Date of Patent: March 30, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Takeshi Nagase, Shogo Shibazaki, Shinkichi Gama
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Publication number: 20090300443Abstract: A test apparatus includes an up counter, a down counter, a selector that selects either an up counter output from the up counter or a down counter output from the down counter, an inversion circuit that inverts either the counter output selected by the selector or the counter output nonselected by the selector, and a comparison circuit that compares the counter output inverted by the inversion circuit and the other counter output.Type: ApplicationFiled: February 19, 2009Publication date: December 3, 2009Applicant: FUJITSU LIMITEDInventors: Chikahiro Deguchi, Yutaka Sekino, Shogo Shibazaki, Shinkichi Gama, Takeshi Nagase, Hideyuki Negi
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Publication number: 20090296505Abstract: A memory test is performed by sequentially generating a number of n-bit addresses, whose first to k-th bits (1?k?n) are all set to one of two values, 0 or 1, and whose (k+1)th to n-th bits are all set to the other one of the two values, for all k's which range from 1 to n; writing first test data to each of the generated addresses in the memory; reading second test data from each of the addresses in the memory; and comparing the first test data with the second test data.Type: ApplicationFiled: March 17, 2009Publication date: December 3, 2009Applicant: FUJITSU LIMITEDInventors: Shogo Shibazaki, Shinkichi Gama, Hideyuki Negi, Takeshi Nagase, Chikahiro Deguchi, Yutaka Sekino
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Patent number: 7257666Abstract: Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to arrange the memory area.Type: GrantFiled: March 1, 2004Date of Patent: August 14, 2007Assignee: Fujitsu LimitedInventors: Shinpei Komatsu, Yumi Ishii, Tomohiro Hayashi, Shogo Shibazaki, Hiroyuki Itoh, Masaru Takehara
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Publication number: 20070165864Abstract: An encryption/decryption processing unit performs encryption/decryption processing of data transmitted from a host system, and encryption/decryption processing of key data used for encryption/decryption of the data. A key data buffer temporarily stores encrypted key data. A key data buffer temporarily stores unencrypted key data. An external memory interface controls flash memory attached outside, and reads/writes encrypted key data stored in the key data buffer.Type: ApplicationFiled: December 21, 2005Publication date: July 19, 2007Applicant: FUJITSU LIMITEDInventors: Takeshi Nagase, Shogo Shibazaki, Shinkichi Gama
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Patent number: 7076667Abstract: In a storage device for maintaining information when power is OFF and being capable of executing a test process based on test signals, a test terminal inputs the test signals and an instruction part sends a read out instruction for instructing a memory storing secret data to read out data. Moreover, a decoding part decodes whether or not the data read out by the memory in response to the data reading instruction is the secret data stored in the memory and a maintaining part maintains information in a volatile state resulting from the decoding part. Furthermore, a cutting-off part cuts off the test signals input from the test terminal when the maintaining part maintains information indicating that the secret data is stored.Type: GrantFiled: March 17, 2000Date of Patent: July 11, 2006Assignee: Fujitsu LimitedInventors: Shinkichi Gama, Shogo Shibazaki
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Patent number: 6766409Abstract: Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to arrange the memory area.Type: GrantFiled: May 29, 2003Date of Patent: July 20, 2004Assignee: Fujitsu LimitedInventors: Shinpei Komatsu, Yumi Ishii, Tomohiro Hayashi, Shogo Shibazaki, Hiroyuki Itoh, Masaru Takehara
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Publication number: 20030196029Abstract: Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to arrange the memory area.Type: ApplicationFiled: May 29, 2003Publication date: October 16, 2003Applicant: Fujitsu LimitedInventors: Shinpei Komatsu, Yumi Ishii, Tomohiro Hayashi, Shogo Shibazaki, Hiroyuki Itoh, Masaru Takehara
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Patent number: 6625712Abstract: The present invention relates to a method of producing a memory management table that controls memories having a function to hold data at a time of power cut-off and manages identifier information of memory areas which are data storage destinations designated by a logical address issued by a host device. After an initializing process, the host device is immediately notified of canceling of a busy state, without production of the memory management table. Alternatively, only a part of the memory management table is produced and the host device is notified of the canceling of the busy state. After that, until the host device issues a process request, or when the host device is issuing a process request, an incomplete part of the memory management table is completed. Thus, the memory management table can be completed.Type: GrantFiled: March 9, 2001Date of Patent: September 23, 2003Assignee: Fujitsu LimitedInventors: Shogo Shibazaki, Takeshi Nagase
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Patent number: 6584579Abstract: Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode tab. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to rearrange the memory area.Type: GrantFiled: October 17, 2000Date of Patent: June 24, 2003Assignee: Fujitsu LimitedInventors: Shinpei Komatsu, Yumi Ishii, Tomohiro Hayashi, Shogo Shibazaki, Hiroyuki Itoh, Masaru Takehara
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Publication number: 20010014933Abstract: The present invention relates to a method of producing a memory management table that controls memories having a function to hold data at a time of power cut-off and manages identifier information of memory areas which are data storage destinations designated by a logical address issued by a host device. After an initializing process, the host device is immediately notified of canceling of a busy state, without production of the memory management table. Alternatively, only a part of the memory management table is produced and the host device is notified of the canceling of the busy state. After that, until the host device issues a process request, or when the host device is issuing a process request, an incomplete part of the memory management table is completed. Thus, the memory management table can be completed.Type: ApplicationFiled: March 9, 2001Publication date: August 16, 2001Inventors: Shogo Shibazaki, Takeshi Nagase
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Patent number: 6161163Abstract: Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to rearrange the memory area.Type: GrantFiled: August 30, 1999Date of Patent: December 12, 2000Assignee: Fujitsu LimitedInventors: Shinpei Komatsu, Yumi Ishii, Tomohiro Hayashi, Shogo Shibazaki, Hiroyuki Itoh, Masaru Takehara
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Patent number: 6125424Abstract: Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to rearrange the memory area.Type: GrantFiled: January 22, 1998Date of Patent: September 26, 2000Assignee: Fujitsu LimitedInventors: Shinpei Komatsu, Yumi Ishii, Tomohiro Hayashi, Shogo Shibazaki, Hiroyuki Itoh, Masaru Takehara
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Patent number: 6118312Abstract: A clock circuit which selectively outputs a clock signal of a frequency equal to an integer multiple of a frequency of a master clock signal includes a setting circuit which sets a value corresponding to a target frequency of the clock signal, a counting circuit which counts pulses of the master clock signal, and an extracting circuit which extracts a pulse of the master clock signal each time a counter value of the counting circuit becomes equal to the value set by the setting circuit.Type: GrantFiled: March 30, 1999Date of Patent: September 12, 2000Assignee: Fujitsu LimitedInventor: Shogo Shibazaki
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Patent number: 5983312Abstract: Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to rearrange the memory area.Type: GrantFiled: August 18, 1997Date of Patent: November 9, 1999Assignee: Fujitsu LimitedInventors: Shinpei Komatsu, Yumi Ishii, Tomohiro Hayashi, Shogo Shibazaki, Hiroyuki Itoh, Masaru Takehara
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Patent number: 5809257Abstract: A buffer section, a data holding section and a data selector are connected between memories. When multiple bus lines are to be used, for example, the data selector selects those bus lines where desired data is present, after which the data is held in the data holding section and desired timing adjustment is performed by the buffer section to cope with a timing deviation.Type: GrantFiled: January 11, 1996Date of Patent: September 15, 1998Assignee: Fujitsu LimitedInventor: Shogo Shibazaki
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Patent number: 5802551Abstract: Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to rearrange the memory area.Type: GrantFiled: August 19, 1994Date of Patent: September 1, 1998Assignee: Fujitsu LimitedInventors: Shinpei Komatsu, Yumi Ishii, Tomohiro Hayashi, Shogo Shibazaki, Hiroyuki Itoh, Masaru Takehara