Patents by Inventor Shogo Tajima
Shogo Tajima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7411277Abstract: A shield wiring is provided on a boundary of a target region to be shielded of macros, an inner side of the boundary, an outer side of the boundary, or an inner side and an outer side of the boundary, each being as a black box, so as to surround the target region. This shield wiring is electrically connected to a power supply terminal or a power supply wiring of the macros or the like, or to a power supply wiring on another wiring layer through a contact section, thereby fixing a potential of the shield wiring. An accurate delay value is then obtained by estimating an influence of crosstalk between a wiring in a region where the physical wiring pattern is clear and the shield wiring and also estimating a capacitance produced between the wirings.Type: GrantFiled: March 17, 2003Date of Patent: August 12, 2008Assignee: Fujitsu LimitedInventors: Takashi Eshima, Shogo Tajima
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Patent number: 7146592Abstract: Modules 14 to 18 are disposed in a chip 10, and the module 14 includes a plurality of external buffer cells 20 disposed along the peripheral of the module 14, and an internal circuit 21 disposed inside the plurality of external buffer cells 20. Input and output of signals is made between the internal circuit 21 and the external circuit, through the external buffer cells 20. The output-stage transistor of each external buffer cell has a larger size than the transistor size of the internal circuit 21. The external buffer cells 20 have a driving capability for enabling direct driving of a transistor inside the chip through a wire having the maximum Manhattan length of a module-disposed region in on chip. If the disposed area of the plurality of external buffer cells 20 is not sufficient, the size of the module is enlarged, or repartition is made to reform the modules so that the plurality of external buffer cells 20 have their sufficient disposed area.Type: GrantFiled: January 26, 2005Date of Patent: December 5, 2006Assignee: Fujitsu LimitedInventors: Kenji Suzuki, Toru Osajima, Shogo Tajima, Shigenobu Satoh
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Patent number: 7039890Abstract: An integrated circuit layout method comprising the steps of: laying out a plurality of circuit elements and a plurality of connecting wires connecting the circuit elements, on a chip; generating dummy patterns in regions that lie at an interval of a first distance from the connecting wires; and changing the first distance to a second distance that differs from the first distance, with respect to a part of connecting wires among said plurality of connecting wires. After layout, when a timing inspection is carried out by finding the delay values of the connecting wires through consideration of the dummy patterns, it is possible, with respect to a connecting wire of a path exhibiting a timing error, to adjust the separation distance to the dummy patterns (the width of the dummy pattern prohibition region) to thereby correct the delay value of this wiring path.Type: GrantFiled: February 11, 2003Date of Patent: May 2, 2006Assignee: Fujitsu LimitedInventors: Akihisa Takechi, Shogo Tajima
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Patent number: 6924666Abstract: Modules 14 to 18 are disposed in a chip 10, and the module 14 includes a plurality of external buffer cells 20 disposed along the peripheral of the module 14, and an internal circuit 21 disposed inside the plurality of external buffer cells 20. Input and output of signals is made between the internal circuit 21 and the external circuit, through the external buffer cells 20. The output-stage transistor of each external buffer cell has a larger size than the transistor size of the internal circuit 21. The external buffer cells 20 have a driving capability for enabling direct driving of a transistor inside the chip through a wire having the maximum Manhattan length of a module-disposed region in on chip. If the disposed area of the plurality of external buffer cells 20 is not sufficient, the size of the module is enlarged, or repartition is made to reform the modules so that the plurality of external buffer cells 20 have their sufficient disposed area.Type: GrantFiled: October 3, 2002Date of Patent: August 2, 2005Assignee: Fujitsu LimitedInventors: Kenji Suzuki, Toru Osajima, Shogo Tajima, Shigenobu Satoh
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Publication number: 20050128850Abstract: Modules 14 to 18 are disposed in a chip 10, and the module 14 includes a plurality of external buffer cells 20 disposed along the peripheral of the module 14, and an internal circuit 21 disposed inside the plurality of external buffer cells 20. Input and output of signals is made between the internal circuit 21 and the external circuit, through the external buffer cells 20. The output-stage transistor of each external buffer cell has a larger size than the transistor size of the internal circuit 21. The external buffer cells 20 have a driving capability for enabling direct driving of a transistor inside the chip through a wire having the maximum Manhattan length of a module-disposed region in on chip. If the disposed area of the plurality of external buffer cells 20 is not sufficient, the size of the module is enlarged, or repartition is made to reform the modules so that the plurality of external buffer cells 20 have their sufficient disposed area.Type: ApplicationFiled: January 26, 2005Publication date: June 16, 2005Applicant: Fujitsu LimitedInventors: Kenji Suzuki, Toru Osajima, Shogo Tajima, Shigenobu Satoh
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Publication number: 20030178706Abstract: A shield wiring is provided on a boundary of a target region to be shielded of macros, an inner side of the boundary, an outer side of the boundary, or an inner side and an outer side of the boundary, each being as a black box, so as to surround the target region. This shield wiring is electrically connected to a power supply terminal or a power supply wiring of the macros or the like, or to a power supply wiring on another wiring layer through a contact section, thereby fixing a potential of the shield wiring. An accurate delay value is then obtained by estimating an influence of crosstalk between a wiring in a region where the physical wiring pattern is clear and the shield wiring and also estimating a capacitance produced between the wirings.Type: ApplicationFiled: March 17, 2003Publication date: September 25, 2003Applicant: Fujitsu LimitedInventors: Takashi Eshima, Shogo Tajima
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Publication number: 20030177464Abstract: An integrated circuit layout method comprising the steps of: laying out a plurality of circuit elements and a plurality of connecting wires connecting the circuit elements, on a chip; generating dummy patterns in regions that lie at an interval of a first distance from the connecting wires; and changing the first distance to a second distance that differs from the first distance, with respect to a part of connecting wires among said plurality of connecting wires. After layout, when a timing inspection is carried out by finding the delay values of the connecting wires through consideration of the dummy patterns, it is possible, with respect to a connecting wire of a path exhibiting a timing error, to adjust the separation distance to the dummy patterns (the width of the dummy pattern prohibition region) to thereby correct the delay value of this wiring path.Type: ApplicationFiled: February 11, 2003Publication date: September 18, 2003Applicant: FUJITSU LIMITEDInventors: Akihisa Takechi, Shogo Tajima
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Patent number: 6548902Abstract: A semiconductor integrated circuit device in which wirings in different layers are connected electrically by vias and in which wiring width at a connection terminal is limited to the maximum width. A plurality of vias are arranged annularly in an area where a wiring in a lower layer and a wiring in an upper layer overlap. A pillar is generated in an area surrounded by the plurality of vias. Locating the pillar will narrow wiring width at a connection terminal for making interlayer connection. Furthermore, the plurality of vias arranged around the pillar will ensure a good connection.Type: GrantFiled: July 19, 2001Date of Patent: April 15, 2003Assignee: Fujitsu LimitedInventors: Kenji Suzuki, Shogo Tajima
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Publication number: 20030067326Abstract: Modules 14 to 18 are disposed in a chip 10, and the module 14 includes a plurality of external buffer cells 20 disposed along the peripheral of the module 14, and an internal circuit 21 disposed inside the plurality of external buffer cells 20. Input and output of signals is made between the internal circuit 21 and the external circuit, through the external buffer cells 20. The output-stage transistor of each external buffer cell has a larger size than the transistor size of the internal circuit 21. The external buffer cells 20 have a driving capability for enabling direct driving of a transistor inside the chip through a wire having the maximum Manhattan length of a module-disposed region in on chip. If the disposed area of the plurality of external buffer cells 20 is not sufficient, the size of the module is enlarged, or repartition is made to reform the modules so that the plurality of external buffer cells 20 have their sufficient disposed area.Type: ApplicationFiled: October 3, 2002Publication date: April 10, 2003Applicant: Fujitsu LimitedInventors: Kenji Suzuki, Toru Osajima, Shogo Tajima, Shigenobu Satoh
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Publication number: 20020083407Abstract: A semiconductor integrated circuit device in which wirings in different layers are connected electrically by vias and in which wiring width at a connection terminal is limited to the maximum width. A plurality of vias are arranged annularly in an area where a wiring in a lower layer and a wiring in an upper layer overlap. A pillar is generated in an area surrounded by the plurality of vias. Locating the pillar will narrow wiring width at a connection terminal for making interlayer connection. Furthermore, the plurality of vias arranged around the pillar will ensure a good connection.Type: ApplicationFiled: July 19, 2001Publication date: June 27, 2002Applicant: FUJITSU LIMITEDInventors: Kenji Suzuki, Shogo Tajima