Patents by Inventor Shogo Tanabe

Shogo Tanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dynamic type semiconductor memory device and operation method of the same
    Patent number: 7869292
    Abstract: A dynamic type semiconductor memory device includes a sense amplifier connected with a bit line pair to amplify and sense a voltage difference on the bit line pair; a precharge circuit configured to precharge the bit line pair to a power supply voltage on a lower side in response to a first control signal; a memory cell capacitance having one end which is connected with the bit line pair through a first switch circuit which is controlled in response to a signal on a word line; and a reference cell capacitance having one end which is connected with the bit line pair through a second switch circuit which is controlled in response to a signal on a reference word line. The other end of the memory cell capacitance and the other end of the reference cell capacitance are electrically separated.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: January 11, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Nobumitsu Yano, Shogo Tanabe
  • DYNAMIC TYPE SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD OF THE SAME
    Publication number: 20100008172
    Abstract: A dynamic type semiconductor memory device includes a sense amplifier connected with a bit line pair to amplify and sense a voltage difference on the bit line pair; a precharge circuit configured to precharge the bit line pair to a power supply voltage on a lower side in response to a first control signal; a memory cell capacitance having one end which is connected with the bit line pair through a first switch circuit which is controlled in response to a signal on a word line; and a reference cell capacitance having one end which is connected with the bit line pair through a second switch circuit which is controlled in response to a signal on a reference word line. The other end of the memory cell capacitance and the other end of the reference cell capacitance are electrically separated.
    Type: Application
    Filed: July 14, 2009
    Publication date: January 14, 2010
    Applicant: NEC Electronics Corporation
    Inventors: Nobumitsu Yano, Shogo Tanabe