Patents by Inventor Shogo Yoshida

Shogo Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120298917
    Abstract: Provided is an AM device containing a liquid crystal composition satisfying at least one of characteristics such as a high maximum temperature of a nematic phase, a low minimum temperature of the nematic phase, a small viscosity, a large optical anisotropy, a large positive dielectric anisotropy, a large specific resistance, a high stability to ultraviolet light and a high stability to and heat, or having a suitable balance regarding at least two of the characteristics, and the AM device having a short response time, a large voltage holding ratio, a large contrast ratio, a long service life and so forth; wherein a liquid crystal display device contains a liquid crystal composition having a positive dielectric anisotropy and containing a specific compound having a large positive dielectric anisotropy as a first component and a specific compound having a small viscosity as a second component.
    Type: Application
    Filed: February 1, 2011
    Publication date: November 29, 2012
    Applicants: JNC PETROCHEMICAL CORPORATION, JNC CORPORATION
    Inventors: Norikatsu Hattori, Shogo Yoshida
  • Publication number: 20060065925
    Abstract: A vertical MOSFET includes a gate electrode formed inside a trench in a semiconductor layer, an interlayer insulating film formed above the semiconductor layer, a source electrode formed above the interlayer insulating film and electrically connected to a source region of the semiconductor layer through a conductive plug filled in a contact hole of the interlayer insulating film, and a protection diode having one end electrically connected to the source electrode and another end connected to the gate electrode through a gate metal line and including a plurality of PN junctions. The protection diode is formed inside a depressed portion in the semiconductor layer.
    Type: Application
    Filed: September 26, 2005
    Publication date: March 30, 2006
    Inventor: Shogo Yoshida
  • Patent number: 6388310
    Abstract: The invention provides a semiconductor device with a passivation film provided on a surface thereof, said passivation film comprising a SiON layer in contact with the surface of said semiconductor device, and a Si3N4 layer provided at the outer side of said SiON layer, chraracterized in that said passivation film has an outermost layer of Si3N4 and said outermost layer has a portion in contact with said semiconductor device or the exposed area of said SiON layer is nitrided. The semiconductor device has a high bonding strength between the passivation film and the semiconductor device and high moisture resistance.
    Type: Grant
    Filed: August 27, 1997
    Date of Patent: May 14, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hiroyuki Seto, Shogo Yoshida