Patents by Inventor Shohei HAMADA

Shohei HAMADA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240122819
    Abstract: A hydrogel structure (10) includes: a continuous phase (11) of a first hydrogel; and a dispersion phase (12) of a second hydrogel, the dispersion phase being dispersed in the continuous phase (11). A ratio of a local minimum value of a load after break to a breaking load (a local minimum value of a load after break/a breaking load) of the hydrogel structure (10) is 0.1 or more.
    Type: Application
    Filed: February 5, 2021
    Publication date: April 18, 2024
    Applicant: Kao Corporation
    Inventors: Saki HAMADA, Shohei TOYOTA
  • Publication number: 20240087711
    Abstract: A medication management system, method, and related medicine packaging device and packaged medicine are provided. The exemplary system includes a medication device including a memory unit that stores ID information and an ID transmission unit that transmits the ID information stored in the memory unit. A processing device that has correspondence information in which the ID information is associated with prescription information of a plurality of medicines to be taken together with one medication device and personal information about a patient who takes the plurality of medicines. A detector detects the ID information transmitted from the ID transmission unit and transmits the ID information that has been detected to the processing device, which manages medication based on the ID information that has been received and the correspondence information.
    Type: Application
    Filed: November 25, 2023
    Publication date: March 14, 2024
    Inventors: Takanori NAKAMURA, Shohei MORIKAWA, Kosuke HAMADA, Hiroshi TAKEMURA
  • Publication number: 20230326870
    Abstract: This alignment device aligns a stage 10 and a wafer 50 by comparing alignment images captured by respective two chips of the wafer 50 on the stage 10. The alignment device comprises: the stage 10 that holds the wafer 50; an alignment illumination light source 60 that irradiates the wafer 50 held on the stage 10 with light; an alignment image processing unit 67 that receives light from the wafer 50 and acquires the alignment images; an information input/output unit 4 that inputs and outputs information; and an alignment processing unit 3 that processes information from the image processing unit 67 for alignment and the information input/output unit 4.
    Type: Application
    Filed: August 31, 2020
    Publication date: October 12, 2023
    Inventors: Shohei HAMADA, Hidetoshi NISHIYAMA, Atsushi MIKI
  • Patent number: 10934927
    Abstract: A pre-chamber is formed between the front end of a spark plug attached to the cylinder head and a thin pre-chamber wall sticking out from the inside wall surface of the cylinder head to the inside of a main combustion chamber. The communication holes communicating the inside of the pre-chamber and the inside of the main combustion chamber are formed inside the thin pre-chamber wall. The thin pre-chamber wall is formed into a shape with a cross-sectional area gradually decreasing from the inside wall surface of the cylinder head toward the inside of the main combustion chamber such as a conical shape, frustoconical shape, polygonal conical shape, or polygonal frustoconical shape. A ground side electrode portion of the spark plug is positioned inside the gas pocket, and a discharge is caused between the center electrode sticking out from the front end of the center electrode insulator and the ground side electrode portion at the time of ignition.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: March 2, 2021
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shohei Hamada, Akira Kato, Noriyuki Takada
  • Publication number: 20200165961
    Abstract: A pre-chamber is formed between the front end of a spark plug (15) attached to the cylinder head (3) and a thin pre-chamber wall (11) sticking out from the inside wall surface of the cylinder head (3) to the inside of a main combustion chamber (5). The communication holes (13) communicating the inside of the sub chamber (12) and the inside of the main combustion chamber (5) are formed inside the thin pre-chamber wall (11). The thin pre-chamber wall (11) is formed into a shape with a cross-sectional area gradually decreasing from the inside wall surface of the cylinder head (3) toward the inside of the main combustion chamber (5) such as a conical shape, frustoconical shape, polygonal conical shape, or polygonal frustoconical shape.
    Type: Application
    Filed: September 27, 2019
    Publication date: May 28, 2020
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shohei HAMADA, Akira Kato, Noriyuki Takada
  • Patent number: 10438951
    Abstract: An object of the present invention is to provide a semiconductor device and a manufacturing method thereof that may achieve low power consumption in a digital circuit and reduce influence of noise in an analog circuit. The manufacturing method of the semiconductor device includes a first source/drain forming step of forming a first source region and a first drain region by implanting impurities of a second conductivity type into a digital side second conductivity type impurity layer using a gate electrode and a sidewall as a mask and a second drain/source forming step of forming a second source region and a second drain region by implanting impurities of the second conductivity type into an analog side second conductivity type impurity layer using a gate electrode and a sidewall as a mask more shallowly than the impurities of the second conductivity type implanted in the first source/drain forming step.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: October 8, 2019
    Assignee: ASAHI KASEI MICRODEVICES CORPORATION
    Inventors: Shuntaro Fujii, Tatsushi Yagi, Shohei Hamada
  • Publication number: 20180277438
    Abstract: An object of the present invention is to provide a semiconductor device and a manufacturing method thereof that may achieve low power consumption in a digital circuit and reduce influence of noise in an analog circuit. The manufacturing method of the semiconductor device includes a first source/drain forming step of forming a first source region and a first drain region by implanting impurities of a second conductivity type into a digital side second conductivity type impurity layer using a gate electrode and a sidewall as a mask and a second drain/source forming step of forming a second source region and a second drain region by implanting impurities of the second conductivity type into an analog side second conductivity type impurity layer using a gate electrode and a sidewall as a mask more shallowly than the impurities of the second conductivity type implanted in the first source/drain forming step.
    Type: Application
    Filed: March 14, 2018
    Publication date: September 27, 2018
    Applicant: ASAHI KASEI MICRODEVICES CORPORATION
    Inventors: Shuntaro FUJII, Tatsushi YAGI, Shohei HAMADA