Patents by Inventor Shohei Kumegawa

Shohei Kumegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200350484
    Abstract: An elastomer piezoelectric element is configured by alternately disposing first opposite electrodes and second opposite electrodes, and sandwiching a dielectric layer between each first opposite electrode and the corresponding second opposite electrode. Each of the dielectric layers includes a dielectric elastomer sheet-shaped dielectric portion and a conductive elastomer first common electrode connecting the first opposite electrodes to each other or a conductive elastomer second common electrode connecting the second opposite electrodes to each other. The first common electrode and the second common electrode are provided so as to extend from one main surface to another main surface of the dielectric portion, and are joined to the first opposite electrode and the second opposite electrode, respectively, on a joint surface along the dielectric layer.
    Type: Application
    Filed: August 22, 2018
    Publication date: November 5, 2020
    Inventors: Shohei KUMEGAWA, Genki SAGO, Naoto MATSUNAGA
  • Patent number: 10693032
    Abstract: The seed substrate comprises a base substrate and a base layer comprising a Group III nitride semiconductor formed on the base substrate, which has a high dislocation density region and a low dislocation density region. The planar pattern of the high dislocation density region is a honeycomb pattern. A hollow exists between the base substrate and the low dislocation density region. The object layer is grown through a flux method using the seed substrate. The high dislocation density region is melted back at an initial stage of crystal growth, and thereafter, the object layer is grown on the top surface of the low dislocation density region. A cavity remains between the high dislocation density region and the object layer. The presence of the cavity and the hollow makes easy to peel the object layer from the seed substrate.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: June 23, 2020
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Miki Moriyama, Shiro Yamazaki, Shohei Kumegawa
  • Publication number: 20180097142
    Abstract: The seed substrate comprises a base substrate and a base layer comprising a Group III nitride semiconductor formed on the base substrate, which has a high dislocation density region and a low dislocation density region. The planar pattern of the high dislocation density region is a honeycomb pattern. A hollow exists between the base substrate and the low dislocation density region. The object layer is grown through a flux method using the seed substrate. The high dislocation density region is melted back at an initial stage of crystal growth, and thereafter, the object layer is grown on the top surface of the low dislocation density region. A cavity remains between the high dislocation density region and the object layer. The presence of the cavity and the hollow makes easy to peel the object layer from the seed substrate.
    Type: Application
    Filed: September 25, 2017
    Publication date: April 5, 2018
    Inventors: Miki MORIYAMA, Shiro Yamazaki, Shohei Kumegawa
  • Patent number: 9691610
    Abstract: The present invention provides a method for producing a Group III nitride semiconductor crystal and a GaN substrate, in which the transfer of dislocation density or the occurrence of cracks can be certainly reduced on a growth substrate, and the Group III nitride semiconductor crystal can be easily separated from a seed crystal. A mask layer is formed on a GaN substrate, to thereby form an exposed portion of the GaN substrate, and an unexposed portion of the GaN substrate. Through a flux method, a GaN layer is formed on the exposed portions of the GaN substrate in a molten mixture containing at least Group III metal and Na. At that time, non-crystal portions containing the components of the molten mixture are formed on the mask layer so as to be covered with the GaN layer grown on the GaN substrate and the mask layer.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: June 27, 2017
    Assignee: TOYODA GOSEI CO., LTD
    Inventors: Shohei Kumegawa, Yasuhide Yakushi, Seiji Nagai, Miki Moriyama
  • Publication number: 20170081780
    Abstract: A method for producing a Group III nitride semiconductor single crystal, includes forming a mask layer on an underlayer, to thereby form a seed crystal in which a portion of the underlayer is covered with the mask layer and in which the remaining portion of the underlayer is not covered with the mask layer, etching the remaining portion, and growing a Group III nitride semiconductor single crystal on the seed crystal.
    Type: Application
    Filed: November 30, 2016
    Publication date: March 23, 2017
    Inventors: Seiji NAGAI, Miki MORIYAMA, Shohei KUMEGAWA, Shiro YAMAZAKI
  • Patent number: 9567693
    Abstract: The present invention provides a method for producing a Group III nitride semiconductor single crystal having excellent crystallinity, and a method for producing a GaN substrate having excellent crystallinity, the method including controlling melting back. Specifically, a mask layer is formed on a GaN substrate serving as a growth substrate. Then, a plurality of trenches which penetrate the mask layer and reach the GaN substrate are formed through photolithography. The obtained seed crystal and raw materials of a single crystal are fed to a crucible and subjected to treatment under pressurized and high temperature conditions. Portions of the GaN substrate exposed to the trenches undergo melting back with a flux. Through dissolution of the GaN substrate, the dimensions of the trenches increase, to provide large trenches. The GaN layer is grown from the surface of the mask layer as a starting point.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: February 14, 2017
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Seiji Nagai, Miki Moriyama, Shohei Kumegawa, Shiro Yamazaki
  • Patent number: 9153439
    Abstract: A mask layer is formed on a Ga polarity surface of the GaN substrate as a growth substrate. Subsequently, a protective film PF is formed on a N polarity surface of the GaN substrate. Then, a plurality of concave portions is formed from the mask layer extending to the GaN substrate, to thereby form a seed crystal. The seed crystal is etched in a Na melt, and a plurality of concave portions having a facet plane exposed. The seed crystal and the raw materials are placed in a crucible, and the pressure and temperature inside the crucible are increased. Thus, a target GaN layer is grown in the upward direction on the surface of the mask layer and the lateral direction over the concave portions.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: October 6, 2015
    Assignee: Toyoda Gosei Co., Ltd
    Inventors: Shohei Kumegawa, Yasuhide Yakushi, Seiji Nagai, Miki Moriyama
  • Publication number: 20140363954
    Abstract: A mask layer is formed on a Ga polarity surface of the GaN substrate as a growth substrate. Subsequently, a protective film PF is formed on a N polarity surface of the GaN substrate. Then, a plurality of concave portions is formed from the mask layer extending to the GaN substrate, to thereby form a seed crystal. The seed crystal is etched in a Na melt, and a plurality of concave portions having a facet plane exposed. The seed crystal and the raw materials are placed in a crucible, and the pressure and temperature inside the crucible are increased. Thus, a target GaN layer is grown in the upward direction on the surface of the mask layer and the lateral direction over the concave portions.
    Type: Application
    Filed: June 10, 2014
    Publication date: December 11, 2014
    Inventors: Shohei Kumegawa, Yasuhide Yakushi, Seiji Nagai, Miki Moriyama
  • Publication number: 20140360426
    Abstract: The present invention provides a method for producing a Group III nitride semiconductor crystal and a GaN substrate, in which the transfer of dislocation density or the occurrence of cracks can be certainly reduced on a growth substrate, and the Group III nitride semiconductor crystal can be easily separated from a seed crystal. A mask layer is formed on a GaN substrate, to thereby form an exposed portion of the GaN substrate, and an unexposed portion of the GaN substrate. Through a flux method, a GaN layer is formed on the exposed portions of the GaN substrate in a molten mixture containing at least Group III metal and Na. At that time, non-crystal portions containing the components of the molten mixture are formed on the mask layer so as to be covered with the GaN layer grown on the GaN substrate and the mask layer.
    Type: Application
    Filed: June 3, 2014
    Publication date: December 11, 2014
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Shohei Kumegawa, Yasuhide Yakushi, Seiji Nagai, Miki Moriyama