Abstract: A semiconductor module includes a case accommodating a semiconductor element inside and being entirely molded by a resin, a first terminal placed on a top portion of the case and being a terminal to which a bus bar being a flat and elongated metal conductor is to be attached, a second terminal provided on the top portion of the case and being adjacent to the first terminal, and a rib provided between the first terminal and the second terminal. The rib includes a protrusion protruding toward the bus bar.

Abstract: An internal bus information getting method can get information output onto an internal bus to facilitate detection of a malfunction position in a storage element stored in a microcomputer during execution of a user program. The method includes first, setting a target address specifying a memory access that is expected to cause the built-in storage element to malfunction to a register, by executing an interruption handling program. Next, information output onto the internal bus is latched and held in response to a match between an address output onto the internal bus and the target address set to the register. The latched and held information is then read.

Abstract: In the microcomputer with a phase-locked loop (PLL) circuit incorporated, a counter is cleared when an edge detection signal of an edge detector which receives an externally generated clock signal from outside and detects an edge of the clock signal, performs a count operation of an internal clock signal output from the PLL circuit as a count source, and output a count value. When the count value of the counter exceeds a predetermined set value, the PLL incorporated microcomputer detects that the externally generated clock signal has been interrupted, and outputs an external clock stop detection signal.

Abstract: In a microprocessor having a debug module and a JTAG unit based on the JTAG standards, there is provided a vector switching circuit in the CPU core which can switch a debug interruption vector address to a user space or to a system space. This vector switching circuit switches a debug interruption vector address depending upon the state of a debug module specified by a command inputted from external hardware such as an emulator via the JTAG interface. A user program can easily be debugged by allocating the debug program in the user space even if hardware such as an emulator is not connected to the microprocessor.

Abstract: A reset control apparatus, which carries out reset control in response to an external reset signal, includes a count start signal generating unit for producing a count start signal in response to the external reset signal, a counter for starting counting in response to the count start signal, and a reset signal generating unit for outputting an internal reset signal in response to the external reset signal, and for halting the output of the internal reset signal while the counter counts a predetermined count value. The reset control apparatus can solve a problem of a conventional reset control apparatus in that when the pulse width of the external reset signal passing through a noise canceler is narrower than the period of the clock signal, it cannot sample the signal, and hence cannot generate the internal reset signal.

Abstract: A reset control apparatus, which carries out reset control in response to an external reset signal, includes a count start signal generating unit for producing a count start signal in response to the external reset signal, a counter for starting counting in response to the count start signal, and a reset signal generating unit for outputting an internal reset signal in response to the external reset signal, and for halting the output of the internal reset signal while the counter counts a predetermined count value. The reset control apparatus can solve a problem of a conventional reset control apparatus in that when the pulse width of the external reset signal passing through a noise canceler is narrower than the period of the clock signal, it cannot sample the signal, and hence cannot generate the internal reset signal.

Abstract: In the microcomputer with a phase-locked loop (PLL) circuit incorporated, a counter is cleared when an edge detection signal of an edge detector which receives an externally generated clock signal from outside and detects an edge of the clock signal, performs a count operation of an internal clock signal output from the PLL circuit as a count source, and output a count value. When the count value of the counter exceeds a predetermined set value, the PLL incorporated microcomputer detects that the externally generated clock signal has been interrupted, and outputs an external clock stop detection signal.

Abstract: The microcomputer provides with surroundings where data in a RAM can be monitored on the outside without employing an external bus. When a command requesting accessing to a RAM is received from an external monitor, a real time debugger built in the microcomputer confirms that a CPU is not accessing the RAM, and accesses the RAM. On the other hand, when accessing to an emROM, which emulates an actual ROM, is requested from the monitor, the real time debugger accesses one of emROMs which is not being used by the CPU at present.

Abstract: An input/output pad part <5> comprises an input protection circuit <51> which is connected to an external terminal <OT>, an output buffer <52> which is connected to the input protection circuit <51>, a TTL input detection circuit <53>, a Schmidt type input detection circuit <54> and a voltage conversion part <55>enabling transfer of signals having different voltage levels between the same and an internal circuit. Thus provided is a microcomputer employing different power supply voltages for circuits constructing an input/output part and an internal circuit such as a logic part or a memory part, which is capable of transferring signals of different voltage levels between the internal circuit and the circuits constructing the input/output circuit and performing slew rate control.

Abstract: A microcomputer having a program storing unit (16) separately from a CPU. The program storing unit (16) receives from a host computer (7) a boot program used for loading data into a flash memory (11), and stores the boot program into a RAM (2), when a mode decision circuit (15) makes a decision that a chip mode is an RSIF mode. This solves a problem of a conventional microcomputer in that it must reserve a boot program area in the flash memory in advance to prestore the boot program in the boot program area, and hence the entire area of the flash memory cannot be released as a user program area.