Patents by Inventor Shohei MATSUKAWA

Shohei MATSUKAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device
    Patent number: 10725880
    Abstract: There is a need to detect faults on a path between a memory access circuit and a shared resource, faults in a logic circuit, and faults in the shared resource. A semiconductor device includes: a first memory access circuit; a second memory access circuit to check the first memory access circuit; a memory that outputs a memory address based on a first access address input from the first memory access circuit; a duplexing comparison circuit that compares the first access address with a second access address output from the second memory access circuit; a first address comparison circuit that compares the first access address with the memory address; and an error control circuit that outputs a control signal based on a comparison result from the duplexing comparison circuit and a comparison result from the first address comparison circuit.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: July 28, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shohei Matsukawa
  • SEMICONDUCTOR DEVICE
    Publication number: 20190102271
    Abstract: There is a need to detect faults on a path between a memory access circuit and a shared resource, faults in a logic circuit, and faults in the shared resource. A semiconductor device includes: a first memory access circuit; a second memory access circuit to check the first memory access circuit; a memory that outputs a memory address based on a first access address input from the first memory access circuit; a duplexing comparison circuit that compares the first access address with a second access address output from the second memory access circuit; a first address comparison circuit that compares the first access address with the memory address; and an error control circuit that outputs a control signal based on a comparison result from the duplexing comparison circuit and a comparison result from the first address comparison circuit.
    Type: Application
    Filed: August 9, 2018
    Publication date: April 4, 2019
    Inventor: Shohei MATSUKAWA