Abstract: A control device includes: a power source configured to supply a high frequency power to a treatment instrument configured to treat a living tissue; a detecting circuit configured to sequentially detect a phase difference between a voltage and a current of the high frequency power supplied to the treatment instrument; and a processor configured to control operation of the power source, the processor being configured to sequentially calculate a variation of the phase difference detected by the detecting circuit, compare the calculated variation of the phase difference with a first threshold set for a variation of a phase difference, and perform reduction processing to reduce output of the high frequency power to be supplied to the treatment instrument when it is determined that the calculated variation of the phase difference is equal to or smaller than the first threshold.

Abstract: A treatment device for treating a target tissue includes a drive source having a transducer configured to convert electrical energy to mechanical vibrations, an instrument having a blade connected to the drive source and configured to apply the mechanical vibrations to the target tissue, and a control unit configured to control a supply of electrical energy to the drive source. The control unit is configured to automatically adjust the supply of electrical energy to the drive source in response to a detection of a change in a resonance frequency of the blade. The change in resonance frequency of the blade occurs after the target tissue has been completely cut by the blade.

Abstract: A medical device and a method of operating the same are provided. In a method of operating a medical device for ultrasonic treatment, the medical device including an ultrasonic instrument having a vibration transmission member that vibrates ultrasonically, a power source configured to supply electric energy to the ultrasonic instrument, and a processor including a control unit operably connected to the power source, the method includes: controlling supply of the electric energy to the ultrasonic instrument, obtaining a temperature value related to a temperature of the vibration transmission member, the vibration transmission member being separate from a transducer, and controlling the power source to reduce or stop the supply of electric energy of the power source based on the rate of change of the temperature value.

Abstract: A control device includes: a power source configured to supply a high frequency power to a treatment instrument configured to treat a living tissue; a detecting circuit configured to sequentially detect a phase difference between a voltage and a current of the high frequency power supplied to the treatment instrument; and a processor configured to control operation of the power source, the processor being configured to sequentially calculate a variation of the phase difference detected by the detecting circuit, compare the calculated variation of the phase difference with a first threshold set for a variation of a phase difference, and perform reduction processing to reduce output of the high frequency power to be supplied to the treatment instrument when it is determined that the calculated variation of the phase difference is equal to or smaller than the first threshold.

Abstract: A generator includes a control device including a processor, and outputs electrical energy to a treatment instrument. The processor determines whether a treatment target has been heat-denatured prior to receiving an output command, and, based on determination, selects, as an operation state of the treatment instrument, one of a first mode if it is determined that the treatment target has not been heat-denatured and a second mode if it is determined that the treatment target has been heat-denatured. The processor operates the treatment instrument at the selected operation state by controlling the output of the electrical energy to the treatment instrument.

Abstract: An optical transmission control circuit includes: an analog input section which receives optical transmission states as an analog values; an A/D conversion section which converts the analog values into digital values; a value storage section which stores maximum value of the digital values provided by the A/D conversion section; an output register which outputs a value to a host apparatus; and a control section which controls the maximum value storage section to store the maximum value of the digital values therein and controls the output register to output the maximum value to the host apparatus.

Abstract: A method of controlling a transceiver module which includes a physical-layer integrated circuit having a physical-layer register unit, and a control integrated circuit having a control-side register unit. In the method, the physical-layer register unit is emulated by the control-side register unit and the physical-layer integrated circuit is prohibited from generating a first error signal giving notice of detection of a specific error directly to a higher-layer device. A second error signal is output from the physical-layer integrated circuit to the control integrated circuit, giving notice of a high-speed error associated with communication processing and that is detected by the physical-layer integrated circuit. The high-speed error is specified in response to the outputting of the second error signal. A bit is set in the control-side register unit in response to the specifying of a high speed error and the control integrated circuit delivers to the higher-layer device the second error signal.

Abstract: A method of controlling a transceiver module which includes a physical-layer integrated circuit having a physical-layer register unit, and a control integrated circuit having a control-side register unit. In the method, the physical-layer register unit is emulated by the control-side register unit and the physical-layer integrated circuit is prohibited from generating a first error signal giving notice of detection of a specific error directly to a higher-layer device. A second error signal is output from the physical-layer integrated circuit to the control integrated circuit, giving notice of a high-speed error associated with communication processing and that is detected by the physical-layer integrated circuit. The high-speed error is specified in response to the outputting of the second error signal. A bit is set in the control-side register unit in response to the specifying of a high speed error and the control integrated circuit delivers to the higher-layer device the second error signal.

Abstract: A transceiver module is provided with a transceiver IC (PHY IC) having an XENPAK register group including an status register, and a DCU having an XENPAK register group which emulates the XENPAK register group. The PHY IC has an operation mode in which it does not reply to access to the XENPAK register group by a host while the DCU emulates the structure and function of the XENPAK register group.

Abstract: An optical transmission control circuit includes: an analog input section which receives optical transmissions states as analog values; an A/D conversion section which converts the analog values into digital values; a value storage section which stores maximum value of the digital values provided by the A/D conversion section; an output register which outputs a value to a host apparatus; and a control section which controls the maximum value storage section to store the maximum value of the digital values therein and controls the output register to output the maximum value to the host apparatus.

Abstract: A physical-layer unit carries out startup processing in response to a first reset signal delivered from a host, generates and outputs a second reset signal to a data control unit in consideration of time required for the startup processing, reads data for initial setting stored in a storage unit of the data control unit via a serial bus after a waiting time elapses, the waiting time being preset in consideration of the time required for the data control unit to start up in response to the second reset signal, and writes the read data for initial setting into a data register included in the physical layer unit.

Abstract: A peripheral device is detachably connected to a host device and includes: an electronic component that generates heat; an electrical connector for electrically connecting the electronic component to the host device; a heat transfer device having a first end thermally connected to the electronic component; and a heat transfer connector thermally connecting a second of the heat transfer device to the host device. The heat generated by the electronic component is discharged, or transferred, to the host device side through the heat transfer device and the heat transfer connector.

Abstract: A module has an IC for communication control (a PHY unit) and an EEPROM (or MCU) connected to the PHY unit via an I2C bus. When a software reset is triggered while the PHY unit reads non-volatile register (NVR) data from the EEPROM (or MCU) via the I2C bus, the module causes an I2C interface circuit of the PHY unit to forcedly toggle and send a clock signal to the EEPROM (or MCU) via the I2C bus to make the EEPROM (or MCU) recognize that interrupted communications via the I2C bus are pseudo completed.

Abstract: A peripheral device is detachably connected to a host device and includes: an electronic component that generates heat; an electrical connector for electrically connecting the electronic component to the host device; a heat transfer device having a first end thermally connected to the electronic component; and a heat transfer connector thermally connecting a second of the heat transfer device to the host device. The heat generated by the electronic component is discharged, or transferred, to the host device side through the heat transfer device and the heat transfer connector.

Abstract: A transceiver module includes a transceiver (PHY IC) having a status register and a control register to which whether or not to generate a status signal is set according to the cause of an error, and a DCU having registers which emulate the status and control registers. The PHY IC generates an Unmask signal specifying an error which occurs irrespective of the cause of the error, and outputs it to the DCU. The DCU writes the contents of the status register into a DCU status register as well as the host of the error based on the Unmask signal.

Abstract: A transceiver module is provided with a transceiver IC (PHY IC) having an XENPAK register group including an status register, and a DCU having an XENPAK register group which emulates the XENPAK register group. The PHY IC has an operation mode in which it does not reply to access to the XENPAK register group by a host while the DCU emulates the structure and function of the XENPAK register group.

Abstract: An optical communication module includes a physical-layer unit having a first control unit for receiving a write destination address and NVR data from a host via a serial bus, and for carrying out serial/parallel conversion of the received write destination address and NVR data, and storing them in registers of the first control unit, respectively, and a second control unit for copying the stored write destination address and NVR data to corresponding registers of the second control unit, respectively, and for carrying out parallel/serial conversion of the write destination address and NVR data which are copied to the registers of the second control unit, respectively, and sending them to either an EEPROM or a flash memory of a microcomputer, as well as a write command, via another serial bus to write the NVR data into either the EEPROM or the flash memory of the microcomputer.

Abstract: A module has an IC for communication control (a PHY unit) and an EEPROM (or MCU) connected to the PHY unit via an I2C bus. When a software reset is triggered while the PHY unit reads non-volatile register (NVR) data from the EEPROM (or MCU) via the I2C bus, the module causes an I2C interface circuit of the PHY unit to forcedly toggle and send a clock signal to the EEPROM (or MCU) via the I2C bus to make the EEPROM (or MCU) recognize that interrupted communications via the I2C bus are pseudo completed.

Abstract: A physical-layer unit carries out startup processing in response to a first reset signal delivered from a host, generates and outputs a second reset signal to a data control unit in consideration of time required for the startup processing, reads data for initial setting stored in a storage unit of the data control unit via a serial bus after a waiting time elapses, the waiting time being preset in consideration of the time required for the data control unit to start up in response to the second reset signal, and writes the read data for initial setting into a data register included in the physical layer unit.

Abstract: A data table includes a source pointer indicating a starting address of drawing data, a destination pointer indicating a destination of drawing data to be transferred, and a data length indicating a data length of drawing data to be transferred. Data table may indicate drawing data to be drawn. Thus frames may share drawing data. As such the amount of drawing data can be reduced.