Abstract: A composite integrated semiconductor device. In one embodiment, an input surge/noise absorbing circuit absorbs surge from an input signal, an attenuating circuit attenuates the input signal, and an electrical signal converting circuit converts the input signal to an output signal. The input surge/noise absorbing circuit, the attenuating circuit, and the electrical signal converting circuit together form a unit, and a plurality of these units are arranged in parallel in one semiconductor substrate to form the composite integrated semiconductor device, resulting in a reduction in the number of discrete components mounted on a printed circuit board.

Abstract: A composite integrated semiconductor device. In one embodiment, an input surge/noise absorbing circuit absorbs surge from an input signal, an attenuating circuit attenuates the input signal, and an electrical signal converting circuit converts the input signal to an output signal. The input surge/noise absorbing circuit, the attenuating circuit, and the electrical signal converting circuit together form a unit, and a plurality of these units are arranged in parallel in one semiconductor substrate to form the composite integrated semiconductor device, resulting in a reduction in the number of discrete components mounted on a printed circuit board.

Abstract: A composite integrated semiconductor device. In one embodiment, an input surge/noise absorbing circuit absorbs surge from an input signal, an attenuating/level-shifting circuit attenuates or level-shifts the input signal, and an electrical signal converting circuit converts the input signal to an output signal. The input surge/noise absorbing circuit, the attenuating or level-shifting circuit, and the electrical signal converting circuit together form a unit, and a plurality of these units are arranged in parallel in one semiconductor substrate to form the composite integrated semiconductor device, resulting in a reduction in the number of discrete components mounted on a printed circuit board.

Abstract: A composite integrated semiconductor device. In one embodiment, an input surge/noise absorbing circuit absorbs surge from an input signal, an attenuating/level-shifting circuit attenuates or level-shifts the input signal, and an electrical signal converting circuit converts the input signal to an output signal. The input surge/noise absorbing circuit, the attenuating or level-shifting circuit, and the electrical signal converting circuit together form a unit, and a plurality of these units are arranged in parallel in one semiconductor substrate to form the composite integrated semiconductor device, resulting in a reduction in the number of discrete components mounted on a printed circuit board.

Abstract: A semiconductor wafer is disclosed in which a high concentration impurity layer is formed in a semiconductor wafer to a predetermined depth, in order to electrically connect electrodes formed on the principal face of the wafer without forming trenches and through holes in the wafer. An n++ diffusion region is formed in the dicing region of a semiconductor wafer by ion implanting or diffusion. The diffusion region extends to an n++ layer formed deep in the semiconductor wafer. The width of the n++ diffusion region is made wide enough to account for the blade width of a dicer, so that an n++ diffusion region remains at the outer periphery of each of the chips divided by the dicing operation. Bump electrodes on the wafer surface electrically connect with the n++ layer deep in the semiconductor through the n++ diffusion region.

Abstract: A semiconductor wafer is disclosed in which a high concentration impurity layer is formed in a semiconductor wafer to a predetermined depth, in order to electrically connect electrodes formed on the principal face of the wafer without forming trenches and through holes in the wafer. An n++ diffusion region is formed in the dicing region of a semiconductor wafer by ion implanting or diffusion. The diffusion region extends to an n++ layer formed deep in the semiconductor wafer. The width of the n++ diffusion region is made wide enough to account for the blade width of a dicer, so that an n++ diffusion region remains at the outer periphery of each of the chips divided by the dicing operation. Bump electrodes on the wafer surface electrically connect with the n++ layer deep in the semiconductor through the n++ diffusion region.

Abstract: A composite integrated semiconductor device. In one embodiment, an input surge/noise absorbing circuit absorbs surge from an input signal, an attenuating/level-shifting circuit attenuates or level-shifts the input signal, and an electrical signal converting circuit converts the input signal to an output signal. The input surge/noise absorbing circuit, the attenuating or level-shifting circuit, and the electrical signal converting circuit together form a unit, and a plurality of these units are arranged in parallel in one semiconductor substrate to form the composite integrated semiconductor device, resulting in a reduction in the number of discrete components mounted on a printed circuit board.

Abstract: A MOS type semiconductor apparatus is provided which includes a main MOS type semiconductor device, an internal control circuit connected between a control input terminal (G) and a control input port (g) of the main MOS type semiconductor device, and a protecting device connected between the control input terminal (G) and one of output terminals (S) of the apparatus, for protecting the semiconductor device or internal control circuit against overvoltage. The protecting device includes a first branch including a Zener diode (Z1p) consisting of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and a second branch including a Zener diode (Z21) formed in a surface layer of the semiconductor substrate, and a diode (Z3pr) that consists of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and is connected in series with the Zener diode (Z21) in a reverse direction. The first and second branches are connected in parallel with each other.

Abstract: In an ignition semiconductor device, a self-shut down circuit forcibly turns off an IGBT when an input signal is continuously applied. The self-shut down circuit is formed of a main-current gradual-reduction circuit having a timer circuit, a capacitor, a resistor, and an FET. When the timer circuit, which is actuated when the input signal is input, counts out, the FET is turned on to cause a capacitor, which is connected parallel to a resistor for producing a reference voltage for a current-limiting circuit, to discharge slowly through the resistor, thereby gradually reducing the reference voltage. Correspondingly, the current-limiting circuit reduces the main current to turn off the IGBT. The slow turn-off operation of the IGBT prevents a high voltage from being generated in the ignition coil.

Abstract: A MOS type semiconductor apparatus is provided which includes a main MOS type semiconductor device, an internal control circuit connected between a control input terminal (G) and a control input port (g) of the main MOS type semiconductor device, and a protecting device connected between the control input terminal (G) and one of output terminals (S) of the apparatus, for protecting the semiconductor device or internal control circuit against overvoltage. The protecting device includes a first branch including a Zener diode (Z1p) consisting of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and a second branch including a Zener diode (Z21) formed in a surface layer of the semiconductor substrate, and a diode (Z3pr) that consists of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and is connected in series with the Zener diode (Z21) in a reverse direction. The first and second branches are connected in parallel with each other.

Abstract: A MOS type semiconductor apparatus is provided which includes a main MOS type semiconductor device, an internal control circuit connected between a control input terminal (G) and a control input port (g) of the main MOS type semiconductor device, and a protecting device connected between the control input terminal (G) and one of output terminals (S) of the apparatus, for protecting the semiconductor device or internal control circuit against overvoltage. The protecting device includes a first branch including a Zener diode (Z1p) consisting of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and a second branch including a Zener diode (Z21) formed in a surface layer of the semiconductor substrate, and a diode (Z3pr) that consists of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and is connected in series with the Zener diode (Z21) in a reverse direction. The first and second branches are connected in parallel with each other.

Abstract: A circuit is provided in which a voltage due to a minute current is applied to a gate terminal from a collector terminal when a collector voltage is higher than a gate voltage in an operation of current limitation. Thus, an increase in the collector voltage immediately after the operation of current limitation starts serves to boost the gate voltage. The boosted voltage suppress an abrupt increase in the collector voltage. When the collector voltage is reduced by oscillation, the action of boosting the gate voltage is lowered to suppress the reduction of the collector voltage.

Abstract: A MOS type semiconductor device is provided which includes a series Zener diode array for overvoltage protection, which is provided between source regions and an electrode having substantially the same potential as a drain electrode, and a field insulating film on which the series Zener diode array is provided. The thickness T (.mu.m) of the field insulating film is determined as a function of the clamp voltage V.sub.CE (V) of the series Zener diode array, such that the thickness T is held in the range as represented by: T.gtoreq.2.0.times.10.sup.-3 .times.V.sub.CE. The width W.sub.1 (.mu.m) of a portion of a second-conductivity-type isolation well that is close to the field insulating film on which the series Zener diode array is provided, and the width W.sub.2 (.mu.m) of a portion of the second-conductivity-type isolation well that is close to the field insulating film on which the series Zener diode array is not provided, are determined as a function of the clamp voltage V.sub.

Abstract: The disclosed invention is designed to prevent the oscillation which often occurs in an over-current protection apparatus for an insulated gate controlled transistor. The apparatus improves the response in current detection, to prevent oscillation, and improves protection speed against over-current.

Abstract: In a semiconductor device with a power element on a substrate, a temperature monitor element is formed on the same substrate. In case of thermal overload in the power element, a signal from the temperature monitor element can be used for turning the power element off. For enhanced temperature response, the temperature monitor element is in part surrounded by the power element or/and disposed beneath an integrated, thermally conductive extension of an electrode of the power element.

Abstract: A semiconductor switching device including a first IGBT and a second IGBT connected in parallel The first IGBT has a low saturation voltage and a long fall time, whereas the second IGBT has a high saturation voltage and a short fall time. An input resistor is connected to the gate of the second IGBT, and a common drive signal is applied to a gate of the first IGBT, and to a gate of the second IGBT through the input resistor. The cutoff of the second IGBT is delayed when the first and second IGBTs are driven by the common drive signal so that the semiconductor switching device is turned off in the short fall time of the second IGBT. The switching speed is increased and the switching loss is decreased. Only a single drive circuit is enough for driving the device, enabling the miniaturization and low cost of the driving circuit.

Abstract: A pressure-contact type semiconductor device with pressure-contact electrodes for external connection is disclosed. The pressure-contact electrodes are mounted through an insulating material on a metal substrate having semiconductor elements mounted thereon side-by-side. The pressure-contact electrodes are wire-bonded to the terminals of the semiconductor elements. Flexible insulating sheets are inserted between the metal substrate and the pressure-contact electrode and between the pressure-contact electrodes respectively. The insulating sheets are fixed onto the metal substrate and the pressure-contact electrodes through an adhesive.

Abstract: A switching power supply having an overcurrent protective circuit which includes a detection resistor for detecting the primary current of a transformer to produce a detected voltage, a reference voltage circuit for producing a reference voltage, and an amplifier. The amplifier produces an overcurrent protective signal when the detected voltage exceeds the reference voltage, and supplies the overcurrent protective signal to the control terminal of a switching device which switches the primary current so that a drive signal for the switching device is decreased when an overcurrent of the secondary current occurs. The overcurrent is limited to a value equal to or less than the rated current of the switching power supply without an instantaneous interruption of the power.

Abstract: In a switching transistor control circuit, the switching transistor has a control electrode and first and second main circuit electrodes. A reactor is connected in series with the first main circuit electrode of the switching transistor to receive a main circuit current through the switching transistor. Circuitry is connected to an end of the reactor remote from the first main electrode and to the control electrode of the switching transistor, for supplying an electromotive force to the control electrode which is generated by the reactor as main circuit current decreases when the switching transistor is turned off. A control electrode driving circuit is connected to the control electrode, and is connected to one of the first main circuit electrode and a predetermined intermediate position on the reactor, for supplying a drive signal to the control electrode for selectively turning the switching transistor on and off.

Abstract: A semiconductive device integrated on a single chip and adapted for self-protecting use in control applications, including an insulated gate bipolar transistor (IGBT) useful as a series controller for a load. In the event of a load failure (short), the upward current excursion is inhibited by a control arrangement in which a sensing resistor in the emitter circuit of the IGBT turns on a three-terminal signal shunt across the signal control path of the IGBT. The signal shunt includes a voltage dropping element such as a Zener diode and may also include Zener reverse-voltage protection. The sensing resistor may be placed in the low-current branch of a split-emitter current path of the IGBT. A pulsed constant-amplitude driving signal may be applied to the control signal path of the IGBT through serially-connected NPN and PNP bipolar transistors providing a common driving node connected through a serial impedance to the control signal path of the IGBT and to the signal shunt.