Abstract: Semiconductor memory device includes: a first and second member each extending in a first direction in a boundary part between a first and second block region and arranged in the first direction; a support pillar arranged between the first and second member at the boundary part; conductive layers separated from one another and arranged in a third direction and split by the first and second member, and the support pillar into a first and second portion; and a memory pillar penetrating through the conductive layers. The support pillar includes a lower and upper pillar. A side face of the lower pillar and an extension of a side face of the upper pillar are displaced from each other in a plane based on a second and the third direction.

Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film disposed on the semiconductor substrate, a first conductive film disposed on the first insulating film, a second insulating film disposed on the first conductive film, a second conductive film disposed on the second insulating film, a first electrode disposed on the first conductive film through an opening formed in the second conductive film and the second insulating film, and having a first width, a second electrode that is formed on the first electrode and having a second width, and a wiring layer that is formed on the second electrode. A first width of the first electrode is wider than a second width of the second electrode.

Abstract: A semiconductor device according to an embodiment described below comprises agate electrode disposed sandwiching a gate insulating film, on an active area. The element isolation insulating film comprises: a first element isolation insulating film having a first width; and a second element isolation insulating film having a second width larger than the first width. The first element isolation insulating film includes in an surface thereof a first element isolation trench having a third width, and the second element isolation insulating film includes in an surface thereof a second element isolation trench having a fourth width larger than the third width. The first element isolation trench has disposed therein a third element isolation insulating film, and the second element isolation trench has disposed therein a fourth element isolation insulating film different from the third element isolation insulating film.

Abstract: Method of manufacturing a semiconductor device includes forming, in a first region, a first trench through a second gate electrode film and an interelectrode insulating film, and a second trench partially extending into a sacrificial film in an isolation trench, filling the second trench with a first insulating film; forming a third gate electrode film above the second gate electrode film and into the first trench such that the third gate electrode film contacts the first gate electrode film; etching the third and the second gate electrode film, the interelectrode insulating film, and the first gate electrode film to form select gate electrodes in the first region and a group of memory-cell gate electrodes in the second region; removing the sacrificial film; and forming a second insulating film over the element regions and the isolation trench to define an unfilled gap in the isolation trench below the memory-cell gate electrodes.

Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film disposed on the semiconductor substrate, a first conductive film disposed on the first insulating film, a second insulating film disposed on the first conductive film, a second conductive film disposed on the second insulating film, a first electrode disposed on the first conductive film through an opening formed in the second conductive film and the second insulating film, and having a first width, a second electrode that is formed on the first electrode and having a second width, and a wiring layer that is formed on the second electrode. A first width of the first electrode is wider than a second width of the second electrode.

Abstract: A semiconductor device including a semiconductor substrate having a hook-up region; wirings extending in a first direction above the semiconductor substrate and being aligned with a first spacing between one another, every two wirings forming pairs of wirings, each pair having a first portion being bent in a second direction different from the first direction in the hook-up region, the wirings of each pair being spaced from one another by a first spacing, the pairs being spaced from one another by a second spacing greater than the first spacing; and fringe patterns each being formed on a first side of each of the wirings of each of the pairs, the first side facing the second spacing.

Abstract: Method of manufacturing a semiconductor device includes forming, in a first region, a first trench through a second gate electrode film and an interelectrode insulating film, and a second trench partially extending into a sacrificial film in an isolation trench, filling the second trench with a first insulating film; forming a third gate electrode film above the second gate electrode film and into the first trench such that the third gate electrode film contacts the first gate electrode film; etching the third and the second gate electrode film, the interelectrode insulating film, and the first gate electrode film to form select gate electrodes in the first region and a group of memory-cell gate electrodes in the second region; removing the sacrificial film; and forming a second insulating film over the element regions and the isolation trench to define an unfilled gap in the isolation trench below the memory-cell gate electrodes.

Abstract: A semiconductor device includes a memory cell gate structure having a first gate insulating film, a first gate electrode, a second gate insulating film, and a second gate electrode, a select gate structure having a third gate insulating film and a third gate electrode including a first electrode portion, a second electrode portion, and a third electrode portion between the first electrode portion and the second electrode portion, a first impurity diffusion layer formed in a surface area of the semiconductor substrate and located at a portion which corresponds to an area between the memory cell gate structure and the first electrode portion, and a second impurity diffusion layer formed in a surface area of the semiconductor substrate and located at a portion which corresponds to an area between the first electrode portion and second electrode portion.

Abstract: A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between the first gate electrodes, lowering a top of the first interlayer insulating layer, depositing a second interlayer insulating layer on the first interlayer insulating layer and the first gate electrodes, planarizing a surface of the second interlayer insulating layer, and forming an interconnect layer in the second interlayer insulating layer and a contact plug in the first interlayer insulating layer and the second interlayer insulating layer so that the contact plug is in contact with the interconnect layer and one of the source/drain areas.

Abstract: A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between the first gate electrodes, lowering a top of the first interlayer insulating layer, depositing a second interlayer insulating layer on the first interlayer insulating layer and the first gate electrodes, planarizing a surface of the second interlayer insulating layer, and forming an interconnect layer in the second interlayer insulating layer and a contact plug in the first interlayer insulating layer and the second interlayer insulating layer so that the contact plug is in contact with the interconnect layer and one of the source/drain areas.

Abstract: A semiconductor device includes a memory cell gate structure having a first gate insulating film, a first gate electrode, a second gate insulating film, and a second gate electrode, a select gate structure having a third gate insulating film and a third gate electrode including a first electrode portion, a second electrode portion, and a third electrode portion between the first electrode portion and the second electrode portion, a first impurity diffusion layer formed in a surface area of the semiconductor substrate and located at a portion which corresponds to an area between the memory cell gate structure and the first electrode portion, and a second impurity diffusion layer formed in a surface area of the semiconductor substrate and located at a portion which corresponds to an area between the first electrode portion and second electrode portion.

Abstract: A semiconductor device includes a pair of select gate structures which are opposed to each other and which are formed in a select transistor formation area, each of the select gate structures including a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film, and a pair of memory cell gate structure groups which are formed in a pair of memory cell formation areas between which the select transistor formation area is interposed and each of which has a plurality of memory cell gate structures arranged at the same pitch, the pair of select gate structures having sides which are opposed to each other, and at least the upper portion of each of the opposed sides of the select gate structures being inclined.

Abstract: A semiconductor device includes a memory cell gate structure having a first gate insulating film, a first gate electrode, a second gate insulating film, and a second gate electrode, a select gate structure having a third gate insulating film and a third gate electrode including a first electrode portion, a second electrode portion, and a third electrode portion between the first electrode portion and the second electrode portion, a first impurity diffusion layer formed in a surface area of the semiconductor substrate and located at a portion which corresponds to an area between the memory cell gate structure and the first electrode portion, and a second impurity diffusion layer formed in a surface area of the semiconductor substrate and located at a portion which corresponds to an area between the first electrode portion and second electrode portion.

Abstract: A semiconductor device includes a pair of select gate structures which are opposed to each other and which are formed in a select transistor formation area, each of the select gate structures including a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film, and a pair of memory cell gate structure groups which are formed in a pair of memory cell formation areas between which the select transistor formation area is interposed and each of which has a plurality of memory cell gate structures arranged at the same pitch, the pair of select gate structures having sides which are opposed to each other, and at least the upper portion of each of the opposed sides of the select gate structures being inclined.

Abstract: A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between the first gate electrodes, lowering a top of the first interlayer insulating layer, depositing a second interlayer insulating layer on the first interlayer insulating layer and the first gate electrodes, planarizing a surface of the second interlayer insulating layer, and forming an interconnect layer in the second interlayer insulating layer and a contact plug in the first interlayer insulating layer and the second interlayer insulating layer so that the contact plug is in contact with the interconnect layer and one of the source/drain areas.

Abstract: A semiconductor device includes a semiconductor substrate having a plurality of element regions and a plurality of element isolation regions in a first direction, a plurality of floating gate electrodes formed via a gate insulating film on the respective element regions, an intergate insulating film formed on the floating gate electrodes, a plurality of control gate electrodes formed on the intergate insulating film so as to extend over the adjacent floating gate electrodes, and an element isolation insulating film formed in the element isolation region and having an upper end located higher than the upper surface of the gate insulating film, the element isolation insulating film including a part formed between the control gate electrodes so that the central sidewall of the element isolation insulating film is located lower than the end of the sidewall of the element isolation insulating film.

Abstract: A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between the first gate electrodes, lowering a top of the first interlayer insulating layer, depositing a second interlayer insulating layer on the first interlayer insulating layer and the first gate electrodes, planarizing a surface of the second interlayer insulating layer, and forming an interconnect layer in the second interlayer insulating layer and a contact plug in the first interlayer insulating layer and the second interlayer insulating layer so that the contact plug is in contact with the interconnect layer and one of the source/drain areas.

Abstract: A semiconductor device includes a semiconductor substrate, a first memory cell transistor, a first select gate transistor, a second memory cell transistor, a second select gate transistor, a contact plug, silicon oxide films, and plasma films which are formed as the same layer as the silicon oxide films and are provided above upper surfaces of the first and the third gate electrodes.

Abstract: A semiconductor device includes a semiconductor substrate having a plurality of element regions and a plurality of element isolation regions in a first direction, a plurality of floating gate electrodes formed via a gate insulating film on the respective element regions, an intergate insulating film formed on the floating gate electrodes, a plurality of control gate electrodes formed on the intergate insulating film so as to extend over the adjacent floating gate electrodes, and an element isolation insulating film formed in the element isolation region and having an upper end located higher than the upper surface of the gate insulating film, the element isolation insulating film including a part formed between the control gate electrodes so that the central sidewall of the element isolation insulating film is located lower than the end of the sidewall of the element isolation insulating film.

Abstract: A semiconductor memory device includes a semiconductor substrate having a dummy cell region adjacent to a memory cell region, a plurality of memory cell transistors, a selective gate transistor, a peripheral circuit transistor, a selective gate line, a contact plug, a dummy contact plug formed in an element forming region of the memory cell region adjacent to the selective gate line, and a spacer insulating film formed on a sidewall of the peripheral circuit transistor. The sidewall of the selective gate electrode is formed with no spacer insulating film, and the selective gate line has a sidewall facing an region of the dummy cell region in which the dummy contact plug is formed, except for the sidewall of the selective gate electrode. The sidewall of the selective gate line is formed with a spacer insulating film.