Abstract: A calculation concerning the input of a signal is removed from a branch metric calculation processing on a trellis diagram of an extended partial response class, and the calculation of branch metrics and the selection of survivor paths can be carried out by the subtraction of the survivor paths and the comparison of constants.

Abstract: Digital information including a sync data field and a user data field subsequent thereto is read from a storage media as a digital information signal in an analog signal format. The obtained signal is sampled according to a clock signal and is thereby transformed into a digital information signal in a digital format. In the sync data field, the clock signal is synchronized with the digital information signal by an analog PLL circuit. Thereafter, in the user data field, the clock signal is synchronized with the digital information signal by a digital PLL circuit.

Abstract: A peripheral equipment control LSI interposed between an SCSI bus connected to a main CPU and peripheral equipment such as a file device. The LSI is divided into two major blocks. One block recognizes an SCSI protocol ID signal sent over the SCSI bus. The other block generates a signal that causes the other block to leave a sleep state (low power dissipation mode). In a state in which a command is awaited from the main CPU, the peripheral equipment control LSI allows the block containing the ID recognition part to remain active while the other block is kept in the sleep state. On receiving an ID-based selected (access) signal from the main CPU, the LSI detects the start of an access operation and causes the other block to leave its sleep state and to become active.

Abstract: Reproducing apparatus with an A/D (analog-to-digital) converter, which realizes high-accuracy data sampling, high-speed data transfer, low dissipation power and low cost. PR (partial response) processing is performed by receiving encoded signals, delaying the received signals on the basis of a reference clock, and adding the delayed signals and the received signals in analog signal form. The added signals are converted into digital values on the basis of the reference clock by the A/D converter, and Viterbi decoding is performed on the basis of the converted digital values. Owing to the PR processing which is performed at a stage preceding the A/D converter, a frequency band for the A/D conversion can be lowered, and hence, the high-accuracy data sampling is permitted.

Abstract: A signal processing circuit for a magnetic recording/reproducing apparatus, including at least an AGC, a PLL, a LPF, an equalizer circuit and a detection circuit, wherein a coefficient compensation circuit is formed by defining a constitution of the equalizer circuit, an error detection circuit is provided which operates by receiving input from the detection circuit, and the LSI is formed by a plurality of analog and digital chips, and the analog and digital chips are connected by current-output type D/A converters connected to at least the AGC and the PLL.

Abstract: A playback signal processing circuit for reducing decode errors and enabling high-density digital magnetic recording and a digital magnetic recording reproducing unit using the playback signal processing circuit are provided. An estimated waveform generation circuit uses the decoding result of a PRML channel to generate an ideal playback signal waveform. A subtractor provides a waveform representing a difference between the waveform and an actual playback signal. There is a high probability that error bits will occur at an interval of two or four bits because of the nature of GCR code and maximum-likelihood decoding; in the error state of each bit, one bit is incremented by one with respect to the correct bit value and the other signal bit is decremented by one. From this fact, an error detection circuit discriminates an error difference waveform pattern and an error discrimination circuit detects an error bit interval, whereby an error correction circuit carries out error bit correction.

Abstract: Apparatus for recording and/or reproducing user data recorded on a record medium. The apparatus includes record encoder for converting original user data into encoded user data of a predetermined record code and an error correcting code generator for generating original error correcting code data for correcting an error with respect to the encoded user data. A write unit records the encoded user data and the error correcting code on the record medium. A read unit reads the recorded data and the reproduced data is error corrected so as to provide the original user data.

Abstract: The present invention provides an AD converter which operates at high speed with low power consumption and a magnetic recording/regenerating apparatus using it.The magnetic recording/regenerating apparatus has a current controller for switching the operating current of the comparator of the AD converter and an ADC controller for receiving an instruction of the conversion speed corresponding to the regenerating frequency. When the current controller receives an instruction for decreasing the conversion speed, it puts the operation state of the AD converter into the low power consumption state.

Abstract: A plurality of commands which may be sent sequentially from a host computer are interpreted by a host command interpreter to generate a disk command for each disk unit. When these commands make up an access demand for a single continuous area, they are grouped into a single command, which is executed substantially at the same time at each disk unit. Also, a plurality of RMW processing systems having different command issued to disk units are available. A selection condition is detected from the I/O demand information supplied by a host computer, and an optimum one of a plurality of RMW processing systems is selected and executed on the basis of the selection condition.

Abstract: A magnetic disk recording and reproducing apparatus including a unit for inserting an error correcting code relating to control information in the control information, the control information relating to data, a recording control unit for recording the control information and the data in a recording area of a magnetic disk, the recording area having a plurality of sectors, each of the sectors having an ID area for recording the control information and a data area for recording the data, the data area corresponding to the ID area and being provided adjacent to and behind the ID area in the same sector as the ID area, and an error correcting unit for correcting errors in the control information in the ID area using the error correcting code before the data in the data area corresponding to the ID area and provided in the same sector as the ID area is read or recorded.

Abstract: A phase locked loop circuit having a voltage controlled oscillator for generating a clock signal with a frequency determined by a voltage control signal supplied to the voltage controlled oscillator, an AD-conversion circuit for sampling a target signal with a timing determined by the clock signal and for converting sampled values into digital data, a phase locked loop control circuit for generating control data with values representing values of the digital data, and a DA-conversion circuit having an adjustable conversion characteristic for converting the control data into an analog signal and for outputting the analog signal to the voltage controlled oscillator as the voltage control signal.

Abstract: A peripheral equipment control LSI interposed between an SCSI bus connected to a main CPU and peripheral equipment such as a file device. The LSI is divided into two major blocks. One block recognizes an SCSI protocol ID signal sent over the SCSI bus. The other block generates a signal that causes the other block to leave a sleep state (low power dissipation mode). In a sate in which a command is awaited from the main CPU, the peripheral equipment control LSI allows the block containing the ID recognition part to remain active while the other block is kept in the sleep slate. On receiving an ID-based selected (access) signal from the main CPU, the LSI detects the start of an access operation and causes the other block to leave its sleep state and to become active.

Abstract: The present invention provides an AD converter which operates at high speed with low power consumption and a magnetic recording/regenerating apparatus using the same. The magnetic recording/regenerating apparatus has a current controller for switching the operating current of the comparator of the AD converter and an ADC controller for receiving an instruction of the conversion speed corresponding to the regenerating frequency. When the current controller receives an instruction for decreasing the conversion speed, it puts an operation state of the AD converter into a low power consumption state.

Abstract: A peripheral equipment control LSI interposed between an SCSI bus connected to a main CPU and peripheral equipment such as a file device. The LSI is divided into two major blocks. One block recognizes an SCSI protocol ID signal sent over the SCSI bus. The other block generates a signal that causes the other block to leave a sleep state (low power dissipation mode). In a sate in which a command is awaited from the main CPU, the peripheral equipment control LSI allows the block containing the ID recognition part to remain active while the other block is kept in the sleep state. On receiving an ID-based selected (access) signal from the main CPU, the LSI detects the start of an access operation and causes the other block to leave its sleep state and to become active.

Abstract: A magnetic disk system which records and reproduces data on a magnetic disk at different data transfer rates depending on a track position on the disk includes a transversal waveform equalizing circuit which implements an optimal waveform shaping for a readout waveform. The waveform equalizing circuit consists of a register, a frequency synthesizer, a PLL, and a transversal circuit. The transversal circuit consists of variable delay circuits, variable gain amplifiers, and an adder. The frequency synthesizer produces a write clock signal having a frequency which corresponds to a value stored in the register which depends on the data transfer rate, and the PLL responds to the write clock signal to produce a control signal by which the delay time of the transversal circuit is controlled.

Abstract: A peripheral equipment control LSI interposed between an SCSI bus connected to a main CPU and peripheral equipment such as a file device. The LSI is divided into two major blocks. One block recognizes an SCSI protocol ID signal sent over the SCSI bus. The other block generates a signal that causes the other block to leave a sleep state (low power dissipation mode). In a state in which a command is awaited from the main CPU, the peripheral equipment control LSI allows the block containing the ID recognition part to remain active while the other block is kept in the sleep state. On receiving an ID-based selected (access) signal from the main CPU, the LSI detects the start of an access operation and causes the other block to leave its sleep state and to become active.

Abstract: Pulse detector and a data separator are integrated on a single chip semiconductor integrated circuit. In the pulse detector, an input stage of a gain variable amplifier, which amplifies an input signal applied thereto so as to have a constant peak, includes a bipolar transistor, and a pulse generator for generating a pulse shape signal according to a differential value of an output from the gain variable amplifier includes a Bi-CMOS gate or a CMOS gate. In the data separator, a voltage controlled oscillator for generating a clock signal includes a bipolar transistor. A frequency phase comparator for comparing the pulse shape signal in phases with the clock signal generated by the voltage controlled oscillator to obtain a phase difference, includes a Bi-CMOS gate and a CMOS gate.