Abstract: A numerical control device adapted to control a plurality of transfer machines mounted on a transfer line. The numerical control device is composed of an NC section (13) for controlling the axes of the transfer machines and a PMC section (14) for executing sequence control. The PMC section (14) reads current position data from a current position register (16) of the NC section (13) through a window, and compares the read data with previously set zone data (19). A function instruction (18a) delivers the result of the comparison as a zone signal, and executes a modification control of an execution sequence by using the zone signal. Therefor, a high-accuracy region signal can be set.

Abstract: In an interrupt control circuit for use with one of a plurality of modules connected to a multi master bus (12) which accepts an interrupt request from another module through a multi-master bus (20), an interrupt vector number is generated corresponding to an interrupt source, and is sent to a CPU (22) within the module. In addition to a conventional first vector number generating circuit (18) the control circuit includes a second vector number generating circuit (16) which transforms a vector number (N.sub.2) corresponding to a kind of interrupt when the first vector number (N.sub.

Abstract: A picture processing apparatus inputs window data (W) to look-up tables (TBL) in which operators (G or F) to be applied to pixel data (x) are stored in correlation to the locations of the pixel data. By switching between the operators (G or F) contained in the look-up tables (TBL), window processing corresponding to a data address (i,j) is performed on input pixel data (x.sub.ij).

Abstract: A picture processing apparatus uses coefficient matrix data to perform convolution processing on a time-sharing basis with regard to each item of pixel data of a frame memory (3) which stores plural items of pixel data. When such processing is being performed, the results of addition from the adder (5) are delayed a predetermined period of time by delay device (7), thereby assuring that intermediate processing results may be written in the buffer (9) with certainty. At the same time, a read-out address of the buffer (9) is revised by an amount equivalent to the delay in the write timing, thereby making it possible to speed up the time-sharing convolution processing.

Abstract: The present invention is directed to a picture processing apparatus for painting a picture memory of a CRT display unit or similar apparatus by paint data. In accordance with this picture processing apparatus, a dual-port memory (4) is used as a frame buffer for storing picture information. In order to store paint information in a memory cell array (7), the information is internally transferred from predetermined storage circuit (9) via a data register (8) having a serial input function. The number of times the dual-port memory (4) is accessed from the processor (1) is greatly reduced so that the burden on the processor (1) can be alleviated. It is also possible to shorten the time required for the paint information to be stored in the memory cell array (7).

Abstract: A cathode ray tube (CRT) controller (6) reads out a predetermined picture from a frame memory (2) storing a picture to be processed, and generates a bit pattern with respect to a window memory (5), having a size corresponding to the frame memory (2) and storing a bit pattern which specifies the validity or invalidity of picture processing. The pattern output by the CRT controller (6) controls the processing of the frame memory (2), so that picture processing is executed solely with respect to picture data in an area of the frame memory (2) specified by the bit pattern.

Abstract: A system for coupling a visual sensor processor (B) and a robot controller (A), so that the processing of the whole system is sped up and the configuration of the system is low-cost. To this end, the visual sensor processor (B) and the robot controller (A) are coupled together via a bidirectional high-speed data transfer channel (10, 28, l.sub.1, l.sub.2) for an exchange therebetween of required information. A nonvolatile memory (6) and a serial interface (12) for connection to an external input/output device, are installed in the robot controller (A), and are shared by the visual sensor processor (B) and the robot controller (A) through utilization of the channel.

Abstract: A picture processing apparatus includes a window memory (6) connected to a CRT controller (6) and having a size corresponding to a frame memory (2) storing a picture to be processed. A bit pattern for specifying the validity or invalidity of processing performed by a processor (1) is stored in the window memory (6), and picture processing is performed only with regard to picture data of the bits indicative of validity.

Abstract: A picture processing apparatus is provided which includes a first frame memory for storing digitalized picture information and includes SAMs (serial access memories) which are capable of reading and writing parallel data with respect to the frame memory, whereby the data are transferred to a second frame memory, following an address offset, to copy the picture information. High-speed processing for translating a picture can thus be executed.

Abstract: In a picture processing apparatus, a front porch time (FP) conforming to a picture signal from a particular picture input unit (2) is stored beforehand in a register (R) by a host computer (8). When the picture input unit (2) outputs a horizontal synchronizing signal (HSYNC), the front porch time (FP) from issuance of the horizontal synchronizing signal (HSYNC) until the beginning of a significant picture information interval (PCPD) is calculated by referring to the register (R) and counting down the value from the register. The picture information is then introduced into a picture memory (6) from the calculated beginning of the significant picture information interval (PCPD). The picture processing apparatus may be used for a variety of different picture input units, as the host computer stores the front porch time corresponding to the particular picture input unit to be used in the register (R) prior to picture processing.

Abstract: The present invention is directed to an arithmetic which calculates the spatial product sum of each of a plurality of picture element data stored in a frame memory, through utilization of load coefficients with N rows and N columns stored in a coefficient memory. The results of calculation for pieces of picture element data of one row of the frame memory and load coefficients of one row are added to the contents of shift registers corresponding to picture elements. This operation is repeated N times for different rows of the frame memory and different load coefficients. Thus, the spatial product sum calculation is performed at high speed using a small number of multipliers.

Abstract: Disclosed is an industrial robot having a function for controlling a current of a motor for driving, which comprises a circuit (41) for summing a plurality of input signals to which input signals of speed command, speed feedback, current command and current feedback are supplied, a switching circuit (23) for selectively switching the input of speed command to the inputs of current command and current feedback by a switching command signal and an operational amplifier (38) to which the switched signal is supplied. In this industrial robot, the position control is switched over to the current control by a switching command signal from a robot control device (22), and by the position control, an article to be held is shifted to a predetermined position and by the current control, driving electric motors (Mr, M.theta.

Abstract: A system for controlling a plurality of microprocessors, comprising a common memory which can be selectively switched to exclusive buses which are connected to the plurality of microprocessors, respectively, and a priority control circuit which determines the priority of the microprocessors. According to the system of the present invention, it has a common memory that is selectively connected to the buses, data is transmitted without affecting the operation of the microprocessors on the receiving side, data transfer between the microprocessors having different cycle times is carried out at speeds that are adapted to the cycle times of the individual microprocessors, and the degree of the exclusive use of the bus by the microprocessor is prevented from being reduced when the direct memory access transfer is carried out. Consequently, a system for controlling a plurality of microprocessors having an improved performance is obtained in accordance with the present invention.

Abstract: A method of forming a taper leaf for use in a laminated spring wherein pre-tapering work is first performed by which a terminal portion of a sheet of spring material is transformed in its lateral direction so as to become thinner toward the tip while maintaining the vertical thickness of the sheet or section at the original thickness of the material. Subsequently, the same portion is rolled for tapering in a vertical direction.