Patents by Inventor Shoichi Takamizawa

Shoichi Takamizawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220077287
    Abstract: An epitaxial nitride semiconductor is formed over a buffer layer and over a silicon single crystal substrate. A misfit dislocation layer in the silicon single crystal substrate mitigates distortion due to lattice mismatch generated during epitaxial growth of the nitride semiconductor and thermal distortion due to difference in the thermal expansion coefficient occurring during the cooling process after epitaxial growth of the nitride semiconductor. The resulting nitride semiconductor substrate has excellent crystallinity without the occurrence of cracks or large warpage.
    Type: Application
    Filed: September 13, 2021
    Publication date: March 10, 2022
    Inventor: Shoichi Takamizawa
  • Patent number: 9127376
    Abstract: The present invention provides a method for manufacturing a nitride semiconductor self-supporting substrate and a nitride semiconductor self-supporting substrate manufactured by this manufacturing method, the method including at least: a step of preparing a nitride semiconductor self-supporting substrate serving as a seed substrate; a step of epitaxially growing the same type of nitride semiconductor as the seed substrate on the seed substrate; and a step of slicing an epitaxially grown substrate subjected to the epitaxial growth into two pieces in parallel to an epitaxial growth surface. As a result, there is provided a method for manufacturing a large-diameter nitride semiconductor self-supporting substrate having an excellent crystal quality and small warp with good productivity at a low cost, etc.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: September 8, 2015
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Shoichi Takamizawa, Masataka Watanabe
  • Publication number: 20100001376
    Abstract: The present invention provides a method for manufacturing a nitride semiconductor self-supporting substrate and a nitride semiconductor self-supporting substrate manufactured by this manufacturing method, the method including at least: a step of preparing a nitride semiconductor self-supporting substrate serving as a seed substrate; a step of epitaxially growing the same type of nitride semiconductor as the seed substrate on the seed substrate; and a step of slicing an epitaxially grown substrate subjected to the epitaxial growth into two pieces in parallel to an epitaxial growth surface. As a result, there is provided a method for manufacturing a large-diameter nitride semiconductor self-supporting substrate having an excellent crystal quality and small warp with good productivity at a low cost, etc.
    Type: Application
    Filed: December 5, 2007
    Publication date: January 7, 2010
    Applicant: SHIN-ETSU HANDOTAI CO., LTD
    Inventors: Shoichi Takamizawa, Masataka Watanabe
  • Patent number: 7214271
    Abstract: A silicon single crystal wafer process apparatus (10) having: a process chamber (11); a susceptor (12) which is disposed in the process chamber (11), and on an upper surface of which the silicon single crystal wafer (19) is placed; and a lift pin (14) which is provided to be capable of a going up and down operation with respect to the susceptor (12), for attaching or detaching the silicon single crystal wafer (19) to or from the susceptor (12) with the going up and down operation, in a state to support the silicon single crystal wafer (19) from a lower surface side, wherein the lift pin (14) is subjected to polishing on a contact end surface (14d) which contacts with a rear surface of the silicon single crystal wafer (19).
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: May 8, 2007
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Ryuji Kono, Shoichi Takamizawa
  • Publication number: 20040241992
    Abstract: A silicon single crystal wafer process apparatus (10) having: a process chamber (11); a susceptor (12) which is disposed in the process chamber (11), and on an upper surface of which the silicon single crystal wafer (19) is placed; and a lift pin (14) which is provided to be capable of a going up and down operation with respect to the susceptor (12), for attaching or detaching the silicon single crystal wafer (19) to or from the susceptor (12) with the going up and down operation, in a state to support the silicon single crystal wafer (19) from a lower surface side, wherein the lift pin (14) is subjected to polishing on a contact end surface (14d) which contacts with a rear surface of the silicon single crystal wafer (19).
    Type: Application
    Filed: March 18, 2004
    Publication date: December 2, 2004
    Inventors: Ryuji Kono, Shoichi Takamizawa
  • Patent number: 5998283
    Abstract: In a silicon wafer having a CVD film formed on one main face and having the other main face mirror-polished, the components and/or composition of the CVD film change in the thicknesswise direction of the film. This makes it possible to provide a silicon wafer having a thin film provided on the back surface, which thin film has excellent and persistent gettering capability that can remove a greater variety of types of elements and can prevent autodoping.
    Type: Grant
    Filed: August 11, 1997
    Date of Patent: December 7, 1999
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Shoichi Takamizawa, Norihiro Kobayashi
  • Patent number: 5993493
    Abstract: Two or more processes selected from heat treatment for anihilation of oxygen donors, formation of a gettering region, and formation of a dopant-volatilization-prevention film are simultaneously performed in a common apparatus in accordance with the specifications of silicon wafers to be manufactured. Therefore, productivity can be improved.
    Type: Grant
    Filed: August 13, 1997
    Date of Patent: November 30, 1999
    Assignee: Shin-etsu Handotai Co., Ltd.
    Inventors: Shoichi Takamizawa, Norihiro Kobayashi
  • Patent number: 5970365
    Abstract: A silicon wafer has an amorphous silicon layer formed on one main surface thereof. The amorphous silicon layer is formed by plasma chemical vapor deposition. The silicon wafer has a gettering layer that possesses high gettering capability and enhanced continuance of the gettering capability. Moreover, the stress acting on the silicon wafer due to the gettering layer is reduced so that the warpage of the silicon wafer decreases. The silicon wafer can be manufactured with high productivity.
    Type: Grant
    Filed: March 24, 1997
    Date of Patent: October 19, 1999
    Assignee: Shin-Etsu Handotai., Ltd.
    Inventors: Shoichi Takamizawa, Norihiro Kobayashi
  • Patent number: 5899744
    Abstract: There is disclosed a method of manufacturing a semiconductor wafer which includes at least a slicing process for slicing a semiconductor monocrystalline ingot in order to obtain a disc-shaped semiconductor wafer. In the method, the sliced semiconductor wafer is etched before being transported to a subsequent process. Even when a monocrystalline ingot having a large diameter is sliced through use of a wire saw, the method prevents generation of breakage, cracks, chips, or the like in processes subsequent to the slicing process, thereby enabling production of large-diameter wafers with high productivity and high yield through utilization of the advantage of the wire saw in slicing a large-diameter monocrystalline ingot; i.e., high cutting speed and a small amount of slicing stock removal.
    Type: Grant
    Filed: December 16, 1997
    Date of Patent: May 4, 1999
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Kohei Toyama, Shoichi Takamizawa, Kaneyoshi Aramaki