Abstract: A transmission device includes: parallel/serial conversion units; a clock signal transmission unit; a known-parallel data generation unit for inputting known-parallel data to the parallel/serial conversion units; a clock shift unit for sequentially shifting a clock signal, which is outputted from the clock signal transmission unit, by 1 UI of a data signal; sampling units for sampling data signals obtained by serializing the known-parallel data, in accordance with the clock signal shifted by 1 UI; and a diagnostic processing unit for making a diagnosis as to whether the transmission device is operating normally by comparing sampling results with the known-parallel data, and outputting a result of the diagnosis.

Abstract: A transmission device includes: parallel/serial conversion units; a clock signal transmission unit; a known-parallel data generation unit for inputting known-parallel data to the parallel/serial conversion units; a clock shift unit for sequentially shifting a clock signal, which is outputted from the clock signal transmission unit, by 1 UI of a data signal; sampling units for sampling data signals obtained by serializing the known-parallel data, in accordance with the clock signal shifted by 1 UI; and a diagnostic processing unit for making a diagnosis as to whether the transmission device is operating normally by comparing sampling results with the known-parallel data, and outputting a result of the diagnosis.

Abstract: The signal detection circuit of the present invention includes: a comparison section for comparing the absolute value of a voltage of an input differential signal with a threshold voltage corresponding to a first detection level adjustment signal to detect presence/absence of an input signal and outputting a detection signal indicating the detection result; a threshold adjustment control section for generating the first detection level adjustment signal in response to the detection signal and outputting the generated signal; and a detection section for detecting whether or not the level of the detection signal changes repeatedly.

Abstract: The signal detection circuit of the present invention includes: a comparison section for comparing the absolute value of a voltage of an input differential signal with a threshold voltage corresponding to a first detection level adjustment signal to detect presence/absence of an input signal and outputting a detection signal indicating the detection result; a threshold adjustment control section for generating the first detection level adjustment signal in response to the detection signal and outputting the generated signal; and a detection section for detecting whether or not the level of the detection signal changes repeatedly.

Abstract: A clock recovery unit for generating a clock signal corresponding to an asynchronous data signal.

Abstract: A receiver unit for receiving asynchronous digital data signals.

Abstract: A clock recovery unit for generating a clock signal corresponding to an asynchronous data signal.

Abstract: Disclosed is an output driver for driving a universal serial bus. The driver includes a first pull-up circuit, a second pull-up circuit, and a crossover detection circuit. The driver uses the first pull-up circuit to drive the output up to first predetermined voltage. The crossover detection circuit detects the first predetermined voltage and switches to driving the output with the second pull-up circuit. The second pull-up circuit drives output up to a second predetermined target voltage. By driving the output up to only the target voltage using the second pull-up circuit, the likelihood of oscillations about the target voltage can be reduced.

Abstract: An output driver comprising pull-up and pull-down transistors coupled to a pad, each transistor comprising a first terminal, a second terminal, and a third terminal, the output driver further comprising voltage response circuits coupled to the transistors and to the pad, the voltage response circuits modifying a voltage difference between the first terminal and the second terminal of the transistors in response to a change in a voltage difference between the third terminal and the second terminal of the transistors for maintaining a desirable output current level during transitions of a signal.

Abstract: In an output circuit having an input/output terminal, first and second p-channel MOS transistors are serially connected between a power supply and the input/output terminal. An enable signal and an input signal are supplied to an NAND circuit. The gate of the second p-channel MOS transistor is controlled using the output signal of the NAND circuit, thereby outputting a signal through the input/output terminal. If a voltage of a signal received at the input/output terminal exceeds the power supply voltage, a gate controller turns OFF the first p-channel MOS transistor. Accordingly, even if a signal with a voltage higher than the power supply voltage is received at the input/output terminal, the input signal can be output through the input/output terminal with a reduced delay and without generating unnecessary current inside the output circuit or causing any breakdown in a gate oxide film.

Abstract: The input circuit of the present invention includes an NMOSFET. One terminal of the NMOSFET is connected to an input terminal and the gate of the NMOSFET is connected to a power supply terminal via a clamping circuit. A signal, received at the one terminal of the NMOSFET with an amplitude equal to or larger than that of a power supply voltage, is output through the other terminal of the NMOSFET with an amplitude equal to that of the power supply voltage. The input circuit further includes: a gate controller, which is connected to the other terminal of the NMOSFET; and a PMOSFET. One terminal of the PMOSFET is directly connected to the other terminal of the NMOSFET and the gate of the PMOSFET is also connected to the other terminal of the NMOSFET via the gate controller. If the voltage at the other terminal of the NMOSFET is at a high level, the gate controller turns the PMOSFET ON. Alternatively, if the voltage at the other terminal of the NMOSFET is at a low level, the gate controller turns the PMOSFET OFF.

Abstract: An output circuit serving as an interface between an LSI and an external LSI, even though the power voltage of the external LSI is not less than the withstand voltage of the gate oxide layer of each of the MOS transistors forming the output circuit, can supply, from the output unit thereof, a signal of which amplitude is equal to the power voltage of the external LSI without a voltage not less than the withstand voltage above-mentioned applied to the gate oxide layer of each of the MOS transistors. A pull-up circuit for pulling up the potential of the output unit comprises first and second PMOSs being connected in series between the power of the external LSI and the output unit, the first PMOS receiving a pull-up control signal at the gate thereof. A pull-down circuit for pulling down the potential of the output unit comprises first and second NMOSs being connected in series between the output unit and the ground, the first NMOS receiving a pull-down control signal S.sub.d at the gate thereof.