Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: Provided is an oil separator having a high efficiency in removing oil particles of relatively large sizes. A blow-by gas passage of the oil separator (2) includes an upstream passage (18) and a downstream passage (20) extending at an angle to the upstream passage. A separation wall (36) provided in the downstream passage includes a first surface (40, 78) forming an obtuse angle relative to the upstream passage, and a second surface (42) adjoining the first surface on a downstream side thereof and defining a planar surface extending substantially perpendicularly to the upstream passage. The blow-by gas is accelerated in the upstream passage, and the flow direction of the blow-by gas is changed by the first surface without substantially changing the flow speed and without disturbing the flow before the blow-by gas flows along the second surface. At this time, the oil particles in the blow-by gas collide with and are trapped by the second surface owing to the inertia of the oil particles.

Abstract: An oil separator for separating an oil in a blow-by gas, includes a housing forming a flow passage, and defining an annular shoulder face facing a downstream side; a valve member reciprocatable between a blocking position abutting an end face thereof against the annular shoulder face to block the flow passage, and an open position separating the end face from the annular shoulder face to open the flow passage; a spring device urging the valve member toward the blocking position; and a reflux device for refluxing the oil separated from the blow-by gas. The valve member includes a first side face facing a wall face of the flow passage and spaced from the wall face at a predetermined interval. A relation wherein a gap between the end face of the valve member and the annular shoulder face in the open position is narrower than the predetermined interval is always established.

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: Provided is an oil separator having a high efficiency in removing oil particles of relatively large sizes. A blow-by gas passage of the oil separator (2) includes an upstream passage (18) and a downstream passage (20) extending at an angle to the upstream passage. A separation wall (36) provided in the downstream passage includes a first surface (40, 78) forming an obtuse angle relative to the upstream passage, and a second surface (42) adjoining the first surface on a downstream side thereof and defining a planar surface extending substantially perpendicularly to the upstream passage. The blow-by gas is accelerated in the upstream passage, and the flow direction of the blow-by gas is changed by the first surface without substantially changing the flow speed and without disturbing the flow before the blow-by gas flows along the second surface. At this time, the oil particles in the blow-by gas collide with and are trapped by the second surface owing to the inertia of the oil particles.

Abstract: An oil separator for separating an oil in a blow-by gas, includes a housing forming a flow passage, and defining an annular shoulder face facing a downstream side; a valve member reciprocatable between a blocking position abutting an end face thereof against the annular shoulder face to block the flow passage, and an open position separating the end face from the annular shoulder face to open the flow passage; a spring device urging the valve member toward the blocking position; and a reflux device for refluxing the oil separated from the blow-by gas. The valve member includes a first side face facing a wall face of the flow passage and spaced from the wall face at a predetermined interval. A relation wherein a gap between the end face of the valve member and the annular shoulder face in the open position is narrower than the predetermined interval is always established.

Abstract: According to one embodiment, a semiconductor device includes a first sequencer and a second sequencer. The first sequencer operates at a first frequency. The second sequencer operates at a second frequency that is higher than the first frequency. In the first mode, the first sequencer operates in accordance with an instruction received from an external apparatus, and the second sequencer operates under control of the first sequencer. In the second mode, the second sequencer operates in accordance with an instruction received from the external apparatus, and the operation of the first sequencer is stopped.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory configured to receive a first clock and including a first buffer configured to perform a data input operation and a data output operation, a second memory including a second buffer configured to perform a data input operation and a data output operation, and a data bus configured to connect the first buffer and the second buffer. The first memory transfers a second clock to the second memory using the first clock. The first buffer transfers data to the second memory in response to the first clock. The second buffer receives the data from the first buffer in response to the second clock.

Abstract: A memory device including, a nonvolatile memory which stores a step item, a parameter start address, and a parameter which has an address corresponding to the parameter start address and defines the step item, and a controller which performs, on the nonvolatile memory, a test step corresponding to the step item defined by the parameter, the controller being formed in the same chip as the nonvolatile memory.

Abstract: p-Cresol is produced in one step by direct oxidation of p-tolualdehyde with a peroxide in formic acid as a solvent while keeping 3 to 15% by weight of water in formic acid on the basis of formic acid and a reaction temperature in a range of 50.degree. to 150.degree. C.