Patents by Inventor Shoii Shukuri

Shoii Shukuri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Nonvolatile semiconductor memory device
    Patent number: 8339862
    Abstract: According to an aspect of the present invention, it is provided: a nonvolatile semiconductor memory device comprising: a plurality of bit lines arranged in a first direction; a plurality of source lines arranged in the first direction, the plurality of source lines being parallel to the plurality of bit lines, the plurality of source lines being distinct from the plurality of bit lines; a plurality of memory gate lines arranged in a second direction perpendicular to the first direction; a plurality of memory cells arranged in a matrix, each of the plurality of memory cells including a p type MIS nonvolatile transistor having a first terminal, a second terminal, a channel between the first terminal and the second terminal, a gate insulation film formed on the channel, a gate electrode connected to one corresponding memory gate line of the plurality of memory gate lines, and a carrier storage layer formed between the gate insulation film and the gate electrode, the first terminal being connected to one correspo
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: December 25, 2012
    Assignee: Genusion, Inc.
    Inventors: Natsuo Aiika, Shoii Shukuri, Satoshi Shimizu, Taku Ogura
  • Nonvolatile Semiconductor Memory Device
    Publication number: 20090161439
    Abstract: According to an aspect of the present invention, it is provided: a nonvolatile semiconductor memory device comprising: a plurality of bit lines arranged in a first direction; a plurality of source lines arranged in the first direction, the plurality of source lines being parallel to the plurality of bit lines, the plurality of source lines being distinct from the plurality of bit lines; a plurality of memory gate lines arranged in a second direction perpendicular to the first direction; a plurality of memory cells arranged in a matrix, each of the plurality of memory cells including a p type MIS nonvolatile transistor having a first terminal, a second terminal, a channel between the first terminal and the second terminal, a gate insulation film formed on the channel, a gate electrode connected to one corresponding memory gate line of the plurality of memory gate lines, and a carrier storage layer formed between the gate insulation film and the gate electrode, the first terminal being connected to one correspo
    Type: Application
    Filed: December 24, 2008
    Publication date: June 25, 2009
    Applicant: Genusion, Inc.
    Inventors: Natsuo Aiika, Shoii Shukuri, Satoshi Shimizu, Taku Ogura