Abstract: A memory device of the invention has a P type substrate, a first drain area of N type formed in the substrate, a second drain area of N type formed in the substrate close to the first drain area, and a source area of N.sup.+ type formed around the first and second drain areas so that the source area continuously surrounds the drain areas from three sides, e.g., the right, left and top sides of these areas. The combination of the closed arrangement of the drain areas and the surrounding arrangement of the source area decreases minority carriers generated around the drain areas and prevents unbalanced carrier absorption of the drain areas, thereby suppressing the occurrence of a soft error.

Abstract: A semiconductor integrated circuit device has circuits for protecting an input section against an external surge. The device comprises an input terminal, a first resistor connected at one end to the input terminal and a first protective circuit connected between the other end of the first resistor and a reference voltage source for accelerating the discharge of an input surge. The first protective circuit includes a first MOS transistor and a resistor element connected in series to the source-drain path of the first MOS transistor. The integrated circuit further comprises a second resistor connected at one end to the other end of the first resistor, a second protective circuit connected between the other end of the second resistor and the reference voltage source for lowering the potential at the node of the other end of the first resistor and one end of the second resistor, whenever the potential is abnormally high due to the input surge, and a second MOS transistor included in the input section.

Abstract: An address buffer circuit is provided which has first and second MOS transistors whose current paths are connected in series with each other and whose gates are supplied with input signals of opposite phases, and third and fourth MOS transistors whose current paths are connected in series with each other. The first and third MOS transistors are of I-type. The gate of the third MOS transistor is connected to a junction of the first and second MOS transistors and the gates of the second and fourth MOS transistors are commonly connected. The address buffer circuit further has a MOS transistor which controls the conduction state of the third MOS transistor in response to an external control signal.

Abstract: A semiconductor device having a semiconductor substrate, wherein first and second insulating gate FET transistor connected, respectively, in series with first and second polycrystalline silicon layers acting as loads of first and second inverters are formed. The first polycrystalline silicon layer is provided above a gate electrode of the second insulation gate FET transistor, and the second polycrystalline silicon layer is provided above a gate electrode of the first insulation gate FET transistor.

Abstract: Disclosed is a method of producing semiconductor devices, comprising forming a laminate of a lower poly-Si film and an upper silicon nitride film on the substrate surface in a manner to provide a pattern of electrodes and wiring layer, removing the patterned silicon nitride film except the region in which a conductive layer is brought into contact with the underneath poly-Si film later, subjecting the substrate surface region to thermal oxidation so as to form a silicon oxide film covering the exposed surface of the substrate and the exposed surface of the poly-Si film, and removing the remaining silicon nitride film.

Abstract: A semiconductor integrated circuit having a memory and an adjacent peripheral circuit generating minority carriers which can destroy data in a portion of the memory at low temperatures. The load resistance in the portion is made lower or the storage capacity is made higher in the portion than in the remainder of the memory so that at low temperatures data is not lost and the energy consumption of the circuit is not unduly increased.

Abstract: An MOS transistor circuit contains at least one "zero" threshold mode transistor to provide a power-down function for the circuit. The "zero" threshold mode transistor is connected between an enhancement-mode MOS driver transistor and a depletion-mode MOS load transistor.

Abstract: An electrically erasable nonvolatile memory system comprises nonvolatile memory cells each including one transistor. A plurality of row lines are connected commonly to the control gates of the memory cells arranged in a row direction, respectively. For applying a positive voltage to a selected row line upon data-write or data-read and a negative voltage to a selected row line upon data-erase, a plurality of control circuits are provided. Each control circuit is coupled with a corresponding one of the row lines, with one of outputs of a row decoder selecting a row line and with a control terminal which is commonly coupled to the control circuits. Each control circuit is so constructed as to supply to a corresponding row line with a voltage having a prescribed level corresponding to a voltage level applied to the control terminal.