Patents by Inventor Shoji Azuma
Shoji Azuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10267425Abstract: A diaphragm having chemical resistance is disclosed. The diaphragm includes a membrane portion and a connection portion which enables connection of the membrane portion to another member. The membrane portion is formed of a first material having chemical resistance. The connection portion is formed of a second material whose main material is the same as that of the first material. The membrane portion and the connection portion are directly bonded together.Type: GrantFiled: April 29, 2016Date of Patent: April 23, 2019Assignee: CKD CorporationInventors: Masaki Yoshida, Michio Miyashita, Shoji Azuma, Takayuki Kumagai
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Publication number: 20160319945Abstract: A diaphragm having chemical resistance is disclosed. The diaphragm includes a membrane portion and a connection portion which enables connection of the membrane portion to another member. The membrane portion is formed of a first material having chemical resistance. The connection portion is formed of a second material whose main material is the same as that of the first material. The membrane portion and the connection portion are directly bonded together.Type: ApplicationFiled: April 29, 2016Publication date: November 3, 2016Inventors: Masaki YOSHIDA, Michio MIYASHITA, Shoji AZUMA, Takayuki KUMAGAI
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Patent number: 8735288Abstract: A method of forming a semiconductor device includes forming first and second bumps on a semiconductor substrate, forming first and second penetration electrodes penetrating the semiconductor substrate, forming a first conductive structure making a first electrical path between the first bump and the first penetration electrode, and forming a second conductive structure making a second electrical path between the second bump and the second penetration electrode, the second conductive structure being smaller in resistance value than the first conductive structure.Type: GrantFiled: November 16, 2013Date of Patent: May 27, 2014Inventors: Satoshi Itaya, Kayoko Shibata, Shoji Azuma, Akira Ide
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Publication number: 20140073127Abstract: A method of forming a semiconductor device includes forming first and second bumps on a semiconductor substrate, forming first and second penetration electrodes penetrating the semiconductor substrate, forming a first conductive structure making a first electrical path between the first bump and the first penetration electrode, and forming a second conductive structure making a second electrical path between the second bump and the second penetration electrode, the second conductive structure being smaller in resistance value than the first conductive structure.Type: ApplicationFiled: November 16, 2013Publication date: March 13, 2014Applicant: Elpida Memory, Inc.Inventors: Satoshi Itaya, Kayoko SHIBATA, Shoji AZUMA, Akira IDE
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Patent number: 8604621Abstract: A semiconductor device includes a semiconductor substrate, first and second penetration electrodes each penetrating the semiconductor substrate, a multi-level wiring structure formed on the semiconductor substrate, the multi-level wiring structure including a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level wiring and the upper-level wiring, a first wiring pad formed as the lower-level wiring and electrically connected to the first penetration electrode, a second wiring pad formed as the upper-level wiring, a plurality of first through electrodes each formed in the interlayer insulating film to form an electrical connection between the first and second wiring pads, a third wiring pad formed as the lower-level wiring and electrically connected to the second penetration electrode, a fourth wiring pad formed as the upper-level wiring, and a plurality of second through electrodes each formed in the interlayer insulating film.Type: GrantFiled: December 19, 2012Date of Patent: December 10, 2013Assignee: Elpida Memory, Inc.Inventors: Satoshi Itaya, Kayoko Shibata, Shoji Azuma, Akira Ide
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Patent number: 8350389Abstract: A semiconductor device includes a plurality of core chips and an interface chip that controls the core chips. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and plural pads respectively connected to the through silicon vias. The through silicon vias include a through silicon via of a power source system to which a power source potential or a ground potential is supplied, and a through silicon via of a signal system to which various signals are supplied. Among the pads, at least an size of a pad connected to the through silicon via of the power source system is larger than a size of a pad connected to the through silicon via of the signal system. Therefore, a larger parasitic capacitance can be secured.Type: GrantFiled: October 7, 2010Date of Patent: January 8, 2013Assignee: Elpida Memory, Inc.Inventors: Satoshi Itaya, Kayoko Shibata, Shoji Azuma, Akira Ide
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Publication number: 20120175001Abstract: A liquid chemical discharge valve which includes a diaphragm valve having a contact portion for varying that varies a flow condition between the liquid chemical supply port and the liquid chemical discharge port by manipulating a lift amount, which is a distance between the contact portion and one of the liquid chemical supply port and the liquid chemical discharge port, between a closed valve condition and a maximum lift amount. The liquid chemical discharge valve includes an actuator unit for driving the contact portion in accordance with a supply pressure of the operating gas supplied from the operating gas supply port, to thereby manipulate the lift amount. The actuator unit includes a lift amount limiting unit for limiting the maximum lift amount adjustably.Type: ApplicationFiled: January 5, 2012Publication date: July 12, 2012Applicant: CKD CORPORATIONInventors: Yoshifumi NISHIO, Shoji AZUMA, Toshiki MURATA, Nobuya SUZUKI
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Patent number: 8203149Abstract: A standard cell includes a capacity element which is made up of a first well diffusion layer into which a first conductive impurity is diffused in a region from a surface of a substrate to a predetermined depth, an insulation film which is provided on the first well diffusion layer, and a first dummy pattern which is provided on the insulation film.Type: GrantFiled: April 9, 2009Date of Patent: June 19, 2012Assignee: Elpida Memory, Inc.Inventor: Shoji Azuma
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Publication number: 20110084385Abstract: A semiconductor device includes a plurality of core chips and an interface chip that controls the core chips. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and plural pads respectively connected to the through silicon vias. The through silicon vias include a through silicon via of a power source system to which a power source potential or a ground potential is supplied, and a through silicon via of a signal system to which various signals are supplied. Among the pads, at least an size of a pad connected to the through silicon via of the power source system is larger than a size of a pad connected to the through silicon via of the signal system. Therefore, a larger parasitic capacitance can be secured.Type: ApplicationFiled: October 7, 2010Publication date: April 14, 2011Applicant: Elpida Memeory, Inc.Inventors: Satoshi Itaya, Kayoko Shibata, Shoji Azuma, Akira Ide
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Patent number: 7884478Abstract: In a semiconductor apparatus having a plurality of wiring layers, the semiconductor apparatus includes a bonding pad formed by an uppermost wiring layer, a first-layer plug wire formed by a first lower wiring layer in a region under the bonding pad, and a first conductive plug connecting the bonding pad and the first-layer plug wire. The first-layer plug wire may include a plurality of first-layer plug wires arranged in parallel to one another in a stripe pattern.Type: GrantFiled: February 26, 2007Date of Patent: February 8, 2011Assignee: Elpida Memory, Inc.Inventor: Shoji Azuma
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Publication number: 20090256180Abstract: A standard cell includes a capacity element which is made up of a first well diffusion layer into which a first conductive impurity is diffused in a region from a surface of a substrate to a predetermined depth, an insulation film which is provided on the first well diffusion layer, and a first dummy pattern which is provided on the insulation film.Type: ApplicationFiled: April 9, 2009Publication date: October 15, 2009Applicant: Elpida Memory, Inc.Inventor: Shoji Azuma
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Publication number: 20070200242Abstract: In a semiconductor apparatus having a plurality of wiring layers, the semiconductor apparatus includes a bonding pad formed by an uppermost wiring layer, a first-layer plug wire formed by a first lower wiring layer in a region under the bonding pad, and a first conductive plug connecting the bonding pad and the first-layer plug wire. The first-layer plug wire may include a plurality of first-layer plug wires arranged in parallel to one another in a stripe pattern.Type: ApplicationFiled: February 26, 2007Publication date: August 30, 2007Applicant: ELPIDA MEMORY, INC.Inventor: Shoji Azuma