Patents by Inventor Shoji Hashizume
Shoji Hashizume has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10950527Abstract: A chip mounting portion included in a semiconductor device has a region including a semiconductor chip in plan view. When an average surface roughness of the region is “Ra”, 0.8 ?m?Ra?3.0 ?m holds.Type: GrantFiled: March 4, 2019Date of Patent: March 16, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shoji Hashizume, Yasushi Takahashi
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Patent number: 10896826Abstract: The method of the present invention improves quality and reliability of resin mold-type semiconductor devices. The method includes the steps of placing a lead frame such that cavities of a mold match with device formation regions of the lead frame, respectively, and forming encapsulation bodies that encapsulate semiconductor chips by flowing encapsulating resin into the cavities. The mold with an upper mold half and a lower mold half clamped together has a plurality of first gates that allow the cavities to communicate with a runner, and a dummy-cavity gate that allows a dummy cavity to communicate with the runner. During a resin molding process, from the time when the resin starts flowing into the mold to the time when the encapsulation bodies are formed, an orifice of each cavity gate is larger in size than an orifice of the dummy-cavity gate.Type: GrantFiled: July 30, 2018Date of Patent: January 19, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shoji Hashizume, Shinichi Nishimura
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Patent number: 10811281Abstract: A manufacturing method of a semiconductor device, includes: (a) preparing a lead frame having: a first tie bar extending in a first direction in plan view so as to couple a plurality of first leads to one another; a second tie bar extending in the first direction in plan view so as to couple a plurality of second leads to one another; a coupling portion coupled to the first tie bar and the second tie bar; a first chip mounting portion arranged between the first tie bar and the second tie bar in plan view; and a second chip mounting portion arranged between the first chip mounting portion and the second tie bar in plan view; and (b) after the (a), mounting a first semiconductor chip on the first chip mounting portion and mounting a second semiconductor chip on the second chip mounting portion.Type: GrantFiled: June 26, 2019Date of Patent: October 20, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shoji Hashizume, Keita Takada
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Patent number: 10504869Abstract: To improve a performance of a semiconductor device, a semiconductor device includes a lead electrically coupled to a semiconductor chip via a wire. An inner portion of the lead, the semiconductor chip, and the wire are sealed by a sealing body (a resin sealing body). The wire is bonded to an upper surface of a wire bonding portion of the inner portion of the lead. A metal film is formed on a lower surface of the inner portion of the lead, which is on an opposite side to the upper surface. No metal film is formed on the upper surface of the wire bonding portion.Type: GrantFiled: September 20, 2017Date of Patent: December 10, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shoji Hashizume, Yasushi Takahashi
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Publication number: 20190318939Abstract: A manufacturing method of a semiconductor device, includes: (a) preparing a lead frame having: a first tie bar extending in a first direction in plan view so as to couple a plurality of first leads to one another; a second tie bar extending in the first direction in plan view so as to couple a plurality of second leads to one another; a coupling portion coupled to the first tie bar and the second tie bar; a first chip mounting portion arranged between the first tie bar and the second tie bar in plan view; and a second chip mounting portion arranged between the first chip mounting portion and the second tie bar in plan view; and (b) after the (a), mounting a first semiconductor chip on the first chip mounting portion and mounting a second semiconductor chip on the second chip mounting portion.Type: ApplicationFiled: June 26, 2019Publication date: October 17, 2019Inventors: Shoji HASHIZUME, Keita Takada
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Publication number: 20190311974Abstract: A chip mounting portion included in a semiconductor device has a region including a semiconductor chip in plan view. When an average surface roughness of the region is “Ra”, 0.8 ?m?Ra?3.0 ?m holds.Type: ApplicationFiled: March 4, 2019Publication date: October 10, 2019Inventors: Shoji HASHIZUME, Yasushi TAKAHASHI
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Patent number: 10403513Abstract: In a manufacturing method of a semiconductor device, by arranging a lead in the vicinity of a gate portion serving as a resin injection port of a mold, a void is prevented from remaining within an encapsulation body when two semiconductor chips arranged so as to overlap in the Y direction are encapsulated with resin. Further, a length of an inner lead portion of the lead in the Y direction is greater than a length of an inner lead portion of another lead overlapping a chip mounting portion in the Y direction.Type: GrantFiled: February 20, 2018Date of Patent: September 3, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shoji Hashizume, Keita Takada
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Publication number: 20190122900Abstract: The method of the present invention improves quality and reliability of resin mold-type semiconductor devices. The method includes the steps of placing a lead frame such that cavities of a mold match with device formation regions of the lead frame, respectively, and forming encapsulation bodies that encapsulate semiconductor chips by flowing encapsulating resin into the cavities. The mold with an upper mold half and a lower mold half clamped together has a plurality of first gates that allow the cavities to communicate with a runner, and a dummy-cavity gate that allows a dummy cavity to communicate with the runner. During a resin molding process, from the time when the resin starts flowing into the mold to the time when the encapsulation bodies are formed, an orifice of each cavity gate is larger in size than an orifice of the dummy-cavity gate.Type: ApplicationFiled: July 30, 2018Publication date: April 25, 2019Inventors: Shoji HASHIZUME, Shinichi NISHIMURA
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Patent number: 10153230Abstract: An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a metal plate having an upper surface (first surface), a lower surface (second surface) opposite to the upper surface, and a plurality of side surfaces located between the upper and lower surfaces and having a semiconductor chip mounted thereover. A portion of the metal plate is exposed from a sealing body sealing the semiconductor chip. The exposed portion is covered with a metal film. The side surfaces of the metal plate include a first side surface covered with the sealing body and a side surface (second side surface) provided opposite to the first side surface and exposed from the sealing body. Between the upper and side surfaces of the metal plate, an inclined surface inclined with respect to each of the upper and side surfaces and covered with the metal film is interposed.Type: GrantFiled: November 17, 2017Date of Patent: December 11, 2018Assignee: Renesas Electronics CorporationInventor: Shoji Hashizume
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Publication number: 20180277397Abstract: In a manufacturing method of a semiconductor device, by arranging a lead in the vicinity of a gate portion serving as a resin injection port of a mold, a void is prevented from remaining within an encapsulation body when two semiconductor chips arranged so as to overlap in the Y direction are encapsulated with resin. Further, a length of an inner lead portion of the lead in the Y direction is greater than a length of an inner lead portion of another lead overlapping a chip mounting portion in the Y direction.Type: ApplicationFiled: February 20, 2018Publication date: September 27, 2018Inventors: Shoji HASHIZUME, Keita TAKADA
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Publication number: 20180096961Abstract: To improve a performance of a semiconductor device, a semiconductor device includes a lead electrically coupled to a semiconductor chip via a wire. An inner portion of the lead, the semiconductor chip, and the wire are sealed by a sealing body (a resin sealing body). The wire is bonded to an upper surface of a wire bonding portion of the inner portion of the lead. A metal film is formed on a lower surface of the inner portion of the lead, which is on an opposite side to the upper surface. No metal film is formed on the upper surface of the wire bonding portion.Type: ApplicationFiled: September 20, 2017Publication date: April 5, 2018Inventors: Shoji HASHIZUME, Yasushi TAKAHASHI
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Publication number: 20180076117Abstract: An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a metal plate having an upper surface (first surface), a lower surface (second surface) opposite to the upper surface, and a plurality of side surfaces located between the upper and lower surfaces and having a semiconductor chip mounted thereover. A portion of the metal plate is exposed from a sealing body sealing the semiconductor chip. The exposed portion is covered with a metal film. The side surfaces of the metal plate include a first side surface covered with the sealing body and a side surface (second side surface) provided opposite to the first side surface and exposed from the sealing body. Between the upper and side surfaces of the metal plate, an inclined surface inclined with respect to each of the upper and side surfaces and covered with the metal film is interposed.Type: ApplicationFiled: November 17, 2017Publication date: March 15, 2018Inventor: Shoji HASHIZUME
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Patent number: 9831162Abstract: An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a metal plate having an upper surface (first surface), a lower surface (second surface) opposite to the upper surface, and a plurality of side surfaces located between the upper and lower surfaces and having a semiconductor chip mounted thereover. A portion of the metal plate is exposed from a sealing body sealing the semiconductor chip. The exposed portion is covered with a metal film. The side surfaces of the metal plate include a first side surface covered with the sealing body and a side surface (second side surface) provided opposite to the first side surface and exposed from the sealing body. Between the upper and side surfaces of the metal plate, an inclined surface inclined with respect to each of the upper and side surfaces and covered with the metal film is interposed.Type: GrantFiled: October 23, 2016Date of Patent: November 28, 2017Assignee: Renesas Electronics CorporationInventor: Shoji Hashizume
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Publication number: 20170179011Abstract: An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a metal plate having an upper surface (first surface), a lower surface (second surface) opposite to the upper surface, and a plurality of side surfaces located between the upper and lower surfaces and having a semiconductor chip mounted thereover. A portion of the metal plate is exposed from a sealing body sealing the semiconductor chip. The exposed portion is covered with a metal film. The side surfaces of the metal plate include a first side surface covered with the sealing body and a side surface (second side surface) provided opposite to the first side surface and exposed from the sealing body. Between the upper and side surfaces of the metal plate, an inclined surface inclined with respect to each of the upper and side surfaces and covered with the metal film is interposed.Type: ApplicationFiled: October 23, 2016Publication date: June 22, 2017Inventor: Shoji HASHIZUME
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Patent number: 8729512Abstract: An optical coupling element includes a light emitting element and a light receiving element which receives emitted light from the light emitting element. The optical coupling element contains a silicone resin and includes a light transparent resin which covers the light emitting element and the light receiving element and transmits the signal light emitted from the light emitting element to the light receiving element (for example, a specific light transparent gel resin) and a light reflection resin which covers a circumference of the light transparent resin. To the light transparent resin, a dye which absorbs light having a shorter wavelength than a predetermined wavelength range including a light emitting wavelength of the light emitting element is added in a concentration of 0.7% by weight or less.Type: GrantFiled: February 10, 2012Date of Patent: May 20, 2014Assignee: Renesas Electronics CorporationInventors: Shoji Hashizume, Masami Ebihara
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Publication number: 20120223259Abstract: An optical coupling element includes a light emitting element and a light receiving element which receives emitted light from the light emitting element. The optical coupling element contains a silicone resin and includes a light transparent resin which covers the light emitting element and the light receiving element and transmits the signal light emitted from the light emitting element to the light receiving element (for example, a specific light transparent gel resin) and a light reflection resin which covers a circumference of the light transparent resin. To the light transparent resin, a dye which absorbs light having a shorter wavelength than a predetermined wavelength range including a light emitting wavelength of the light emitting element is added in a concentration of 0.7% by weight or less.Type: ApplicationFiled: February 10, 2012Publication date: September 6, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Shoji HASHIZUME, Masami EBIHARA
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Patent number: 5256900Abstract: A package for semiconductor devices formed by brazing a metallic frame and an insulating substrate having metallized patterns for electrically connecting the electrodes of semiconductor elements mounted thereon to the outside, which can reduce the warp in the package generated during the brazing assembly due to the difference in the coefficients of thermal expansion, and can reduce the cracks in the insulating substrate that tend to be created during the brazing assembly due to the thermal stresses. Through holes are drilled in the metallic frame in more than at least one place of the metallic frame.Type: GrantFiled: May 22, 1991Date of Patent: October 26, 1993Assignee: NEC CorporationInventors: Shoji Hashizume, Masayoshi Nasu