Patents by Inventor Shoji Hashizume

Shoji Hashizume has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10950527
    Abstract: A chip mounting portion included in a semiconductor device has a region including a semiconductor chip in plan view. When an average surface roughness of the region is “Ra”, 0.8 ?m?Ra?3.0 ?m holds.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: March 16, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shoji Hashizume, Yasushi Takahashi
  • Patent number: 10896826
    Abstract: The method of the present invention improves quality and reliability of resin mold-type semiconductor devices. The method includes the steps of placing a lead frame such that cavities of a mold match with device formation regions of the lead frame, respectively, and forming encapsulation bodies that encapsulate semiconductor chips by flowing encapsulating resin into the cavities. The mold with an upper mold half and a lower mold half clamped together has a plurality of first gates that allow the cavities to communicate with a runner, and a dummy-cavity gate that allows a dummy cavity to communicate with the runner. During a resin molding process, from the time when the resin starts flowing into the mold to the time when the encapsulation bodies are formed, an orifice of each cavity gate is larger in size than an orifice of the dummy-cavity gate.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: January 19, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shoji Hashizume, Shinichi Nishimura
  • Patent number: 10811281
    Abstract: A manufacturing method of a semiconductor device, includes: (a) preparing a lead frame having: a first tie bar extending in a first direction in plan view so as to couple a plurality of first leads to one another; a second tie bar extending in the first direction in plan view so as to couple a plurality of second leads to one another; a coupling portion coupled to the first tie bar and the second tie bar; a first chip mounting portion arranged between the first tie bar and the second tie bar in plan view; and a second chip mounting portion arranged between the first chip mounting portion and the second tie bar in plan view; and (b) after the (a), mounting a first semiconductor chip on the first chip mounting portion and mounting a second semiconductor chip on the second chip mounting portion.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: October 20, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shoji Hashizume, Keita Takada
  • Patent number: 10504869
    Abstract: To improve a performance of a semiconductor device, a semiconductor device includes a lead electrically coupled to a semiconductor chip via a wire. An inner portion of the lead, the semiconductor chip, and the wire are sealed by a sealing body (a resin sealing body). The wire is bonded to an upper surface of a wire bonding portion of the inner portion of the lead. A metal film is formed on a lower surface of the inner portion of the lead, which is on an opposite side to the upper surface. No metal film is formed on the upper surface of the wire bonding portion.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: December 10, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shoji Hashizume, Yasushi Takahashi
  • Publication number: 20190318939
    Abstract: A manufacturing method of a semiconductor device, includes: (a) preparing a lead frame having: a first tie bar extending in a first direction in plan view so as to couple a plurality of first leads to one another; a second tie bar extending in the first direction in plan view so as to couple a plurality of second leads to one another; a coupling portion coupled to the first tie bar and the second tie bar; a first chip mounting portion arranged between the first tie bar and the second tie bar in plan view; and a second chip mounting portion arranged between the first chip mounting portion and the second tie bar in plan view; and (b) after the (a), mounting a first semiconductor chip on the first chip mounting portion and mounting a second semiconductor chip on the second chip mounting portion.
    Type: Application
    Filed: June 26, 2019
    Publication date: October 17, 2019
    Inventors: Shoji HASHIZUME, Keita Takada
  • Publication number: 20190311974
    Abstract: A chip mounting portion included in a semiconductor device has a region including a semiconductor chip in plan view. When an average surface roughness of the region is “Ra”, 0.8 ?m?Ra?3.0 ?m holds.
    Type: Application
    Filed: March 4, 2019
    Publication date: October 10, 2019
    Inventors: Shoji HASHIZUME, Yasushi TAKAHASHI
  • Patent number: 10403513
    Abstract: In a manufacturing method of a semiconductor device, by arranging a lead in the vicinity of a gate portion serving as a resin injection port of a mold, a void is prevented from remaining within an encapsulation body when two semiconductor chips arranged so as to overlap in the Y direction are encapsulated with resin. Further, a length of an inner lead portion of the lead in the Y direction is greater than a length of an inner lead portion of another lead overlapping a chip mounting portion in the Y direction.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: September 3, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shoji Hashizume, Keita Takada
  • Publication number: 20190122900
    Abstract: The method of the present invention improves quality and reliability of resin mold-type semiconductor devices. The method includes the steps of placing a lead frame such that cavities of a mold match with device formation regions of the lead frame, respectively, and forming encapsulation bodies that encapsulate semiconductor chips by flowing encapsulating resin into the cavities. The mold with an upper mold half and a lower mold half clamped together has a plurality of first gates that allow the cavities to communicate with a runner, and a dummy-cavity gate that allows a dummy cavity to communicate with the runner. During a resin molding process, from the time when the resin starts flowing into the mold to the time when the encapsulation bodies are formed, an orifice of each cavity gate is larger in size than an orifice of the dummy-cavity gate.
    Type: Application
    Filed: July 30, 2018
    Publication date: April 25, 2019
    Inventors: Shoji HASHIZUME, Shinichi NISHIMURA
  • Patent number: 10153230
    Abstract: An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a metal plate having an upper surface (first surface), a lower surface (second surface) opposite to the upper surface, and a plurality of side surfaces located between the upper and lower surfaces and having a semiconductor chip mounted thereover. A portion of the metal plate is exposed from a sealing body sealing the semiconductor chip. The exposed portion is covered with a metal film. The side surfaces of the metal plate include a first side surface covered with the sealing body and a side surface (second side surface) provided opposite to the first side surface and exposed from the sealing body. Between the upper and side surfaces of the metal plate, an inclined surface inclined with respect to each of the upper and side surfaces and covered with the metal film is interposed.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: December 11, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Shoji Hashizume
  • Publication number: 20180277397
    Abstract: In a manufacturing method of a semiconductor device, by arranging a lead in the vicinity of a gate portion serving as a resin injection port of a mold, a void is prevented from remaining within an encapsulation body when two semiconductor chips arranged so as to overlap in the Y direction are encapsulated with resin. Further, a length of an inner lead portion of the lead in the Y direction is greater than a length of an inner lead portion of another lead overlapping a chip mounting portion in the Y direction.
    Type: Application
    Filed: February 20, 2018
    Publication date: September 27, 2018
    Inventors: Shoji HASHIZUME, Keita TAKADA
  • Publication number: 20180096961
    Abstract: To improve a performance of a semiconductor device, a semiconductor device includes a lead electrically coupled to a semiconductor chip via a wire. An inner portion of the lead, the semiconductor chip, and the wire are sealed by a sealing body (a resin sealing body). The wire is bonded to an upper surface of a wire bonding portion of the inner portion of the lead. A metal film is formed on a lower surface of the inner portion of the lead, which is on an opposite side to the upper surface. No metal film is formed on the upper surface of the wire bonding portion.
    Type: Application
    Filed: September 20, 2017
    Publication date: April 5, 2018
    Inventors: Shoji HASHIZUME, Yasushi TAKAHASHI
  • Publication number: 20180076117
    Abstract: An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a metal plate having an upper surface (first surface), a lower surface (second surface) opposite to the upper surface, and a plurality of side surfaces located between the upper and lower surfaces and having a semiconductor chip mounted thereover. A portion of the metal plate is exposed from a sealing body sealing the semiconductor chip. The exposed portion is covered with a metal film. The side surfaces of the metal plate include a first side surface covered with the sealing body and a side surface (second side surface) provided opposite to the first side surface and exposed from the sealing body. Between the upper and side surfaces of the metal plate, an inclined surface inclined with respect to each of the upper and side surfaces and covered with the metal film is interposed.
    Type: Application
    Filed: November 17, 2017
    Publication date: March 15, 2018
    Inventor: Shoji HASHIZUME
  • Patent number: 9831162
    Abstract: An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a metal plate having an upper surface (first surface), a lower surface (second surface) opposite to the upper surface, and a plurality of side surfaces located between the upper and lower surfaces and having a semiconductor chip mounted thereover. A portion of the metal plate is exposed from a sealing body sealing the semiconductor chip. The exposed portion is covered with a metal film. The side surfaces of the metal plate include a first side surface covered with the sealing body and a side surface (second side surface) provided opposite to the first side surface and exposed from the sealing body. Between the upper and side surfaces of the metal plate, an inclined surface inclined with respect to each of the upper and side surfaces and covered with the metal film is interposed.
    Type: Grant
    Filed: October 23, 2016
    Date of Patent: November 28, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Shoji Hashizume
  • Publication number: 20170179011
    Abstract: An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a metal plate having an upper surface (first surface), a lower surface (second surface) opposite to the upper surface, and a plurality of side surfaces located between the upper and lower surfaces and having a semiconductor chip mounted thereover. A portion of the metal plate is exposed from a sealing body sealing the semiconductor chip. The exposed portion is covered with a metal film. The side surfaces of the metal plate include a first side surface covered with the sealing body and a side surface (second side surface) provided opposite to the first side surface and exposed from the sealing body. Between the upper and side surfaces of the metal plate, an inclined surface inclined with respect to each of the upper and side surfaces and covered with the metal film is interposed.
    Type: Application
    Filed: October 23, 2016
    Publication date: June 22, 2017
    Inventor: Shoji HASHIZUME
  • Patent number: 8729512
    Abstract: An optical coupling element includes a light emitting element and a light receiving element which receives emitted light from the light emitting element. The optical coupling element contains a silicone resin and includes a light transparent resin which covers the light emitting element and the light receiving element and transmits the signal light emitted from the light emitting element to the light receiving element (for example, a specific light transparent gel resin) and a light reflection resin which covers a circumference of the light transparent resin. To the light transparent resin, a dye which absorbs light having a shorter wavelength than a predetermined wavelength range including a light emitting wavelength of the light emitting element is added in a concentration of 0.7% by weight or less.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: May 20, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Shoji Hashizume, Masami Ebihara
  • Publication number: 20120223259
    Abstract: An optical coupling element includes a light emitting element and a light receiving element which receives emitted light from the light emitting element. The optical coupling element contains a silicone resin and includes a light transparent resin which covers the light emitting element and the light receiving element and transmits the signal light emitted from the light emitting element to the light receiving element (for example, a specific light transparent gel resin) and a light reflection resin which covers a circumference of the light transparent resin. To the light transparent resin, a dye which absorbs light having a shorter wavelength than a predetermined wavelength range including a light emitting wavelength of the light emitting element is added in a concentration of 0.7% by weight or less.
    Type: Application
    Filed: February 10, 2012
    Publication date: September 6, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Shoji HASHIZUME, Masami EBIHARA
  • Patent number: 5256900
    Abstract: A package for semiconductor devices formed by brazing a metallic frame and an insulating substrate having metallized patterns for electrically connecting the electrodes of semiconductor elements mounted thereon to the outside, which can reduce the warp in the package generated during the brazing assembly due to the difference in the coefficients of thermal expansion, and can reduce the cracks in the insulating substrate that tend to be created during the brazing assembly due to the thermal stresses. Through holes are drilled in the metallic frame in more than at least one place of the metallic frame.
    Type: Grant
    Filed: May 22, 1991
    Date of Patent: October 26, 1993
    Assignee: NEC Corporation
    Inventors: Shoji Hashizume, Masayoshi Nasu