Abstract: A memory output circuit which can ensure the sufficient width of output data even in the case of high speed memory operation. The output circuit comprises an output section, a driver circuit for controlling the output section in response to a control signal, and a delay circuit adapted to reset the driver circuit when a predetermined time has elapsed from the enabling of the output section.

Abstract: A memory output circuit which can ensure that sufficient width of output data even in the case of high speed memory operation. The output circuit comprises an output section, a driver circuit for controlling the output section in response to a control signal, and a delay circuit adapted to reset the driver circuit when a predetermined time has elapsed from the enabling of the output section.

Abstract: A semiconductor memory device which has improved and flexible writing function of multi-bit data.The memory has a plurality of data access circuits operable in parallel. Each of the data access circuits includes a data terminal and a data input circuit operatively storing write data applied to the data terminal. A detection circuit is connected to the data terminal, which circuit detects whether a write inhibition signal is applied to the data terminal. In response to the output of the detection circuit, a control circuit selectively disenables the data input circuit.

Abstract: Dual port memory which enables consecutive access operations from an arbitrary address. The memory includes a memory array, a random access peripheral circuit for effecting random access to the array, a counter, a setting circuit for setting the counting state of the counter at an optional value, a selection circuit for consecutively selecting the array in response to the output of the counter, and a control circuit for advancing the state of the counter in response to a shift pulse.

Abstract: An improved logic circuit which can maintain a high level of a sampled signal on a data node without reduction in level is disclosed. The circuit comprises supply means for supplying a data node with a power supply voltage and control means responsive to a level of the data node for selectively enabling the supply means.

Abstract: A memory device operable at high-speed and with low power consumption is disclosed. The device in which row address information and column address information are incorporated in synchronism with a row strobe signal and a column strobe signal, respectively, and refresh is effected in response to a row address, comprises a plurality of groups of selection gates for selectively supplying the incorporated column address information to a part of a plurality of column address decoders.