Abstract: In one embodiment, a plant control apparatus controls a power plant. The plant includes a gas turbine, a generator driven by the gas turbine, an exhaust heat recovering boiler to generate first steam by using heat of exhaust gas from the gas turbine, a first steam turbine driven by the first steam, a reheater provided in the boiler and configured to heat exhaust steam from the first steam turbine by the exhaust gas to generate reheat steam, and a second steam turbine driven by the reheat steam. The apparatus includes a first warming-up module to supply second steam from equipment different from the boiler to the first steam turbine to warm up this turbine, before this turbine is started. The apparatus further includes a second warming-up module to supply the second steam to the reheater to warm up the reheater, before the first steam turbine is started.

Abstract: A method for selectively and easily quantifying the L-form and/or D-form amino acids to be measured using an aminoacyl tRNA synthetase (AARS) with high sensitivity, and an amino acid quantification kit. A method for quantifying amino acids (L-AA and/or D-AA) in a sample using an AARS, wherein the amino acids and the AARS are released from an aminoacyl AMP-AARS complex once formed, and they are used again for forming the aminoacyl AMP-AARS complex, so that reaction products such as pyrophosphoric acid to be measured can be ultimately produced up to a molar number larger than that of the amino acids contained in the sample, and an amino acid quantification kit for performing the method.

Abstract: In one embodiment, a plant control apparatus controls a power plant, which includes a gas turbine, a generator driven by the gas turbine, an exhaust heat recovering boiler to generate first steam using heat of exhaust gas from the gas turbine, a steam turbine driven by the first steam, and a clutch to connect a first shaft connected to the gas turbine and generator with a second shaft connected to the steam turbine. The apparatus includes a starting module to start the gas turbine and generator while holding the steam turbine in a stop state, when the clutch is in a released state. The apparatus further includes a warming module to warm the steam turbine by supplying second steam from equipment different from the boiler to the steam turbine in parallel with the starting of the gas turbine and generator, when the clutch is in a released state.

Abstract: In one embodiment, a plant control apparatus controls a power plant, which includes a gas turbine, a generator driven by the gas turbine, an exhaust heat recovering boiler to generate first steam using heat of exhaust gas from the gas turbine, a steam turbine driven by the first steam, and a clutch to connect a first shaft connected to the gas turbine and generator with a second shaft connected to the steam turbine. The apparatus includes a starting module to start the gas turbine and generator while holding the steam turbine in a stop state, when the clutch is in a released state. The apparatus further includes a warming module to warm the steam turbine by supplying second steam from equipment different from the boiler to the steam turbine in parallel with the starting of the gas turbine and generator, when the clutch is in a released state.

Abstract: In one embodiment, a plant control apparatus controls a power plant. The plant includes a gas turbine, a generator driven by the gas turbine, an exhaust heat recovering boiler to generate first steam by using heat of exhaust gas from the gas turbine, a first steam turbine driven by the first steam, a reheater provided in the boiler and configured to heat exhaust steam from the first steam turbine by the exhaust gas to generate reheat steam, and a second steam turbine driven by the reheat steam. The apparatus includes a first warming-up module to supply second steam from equipment different from the boiler to the first steam turbine to warm up this turbine, before this turbine is started. The apparatus further includes a second warming-up module to supply the second steam to the reheater to warm up the reheater, before the first steam turbine is started.

Abstract: [Problem to be solved] It is to provide a method for selectively and easily quantifying the L-form and/or D-form amino acids to be measured using an AARS with high sensitivity, and an amino acid quantification kit. [Solution to Problem] A method for quantifying amino acids (L-AA and/or D-AA) in a sample using an AARS, wherein the amino acids and the AARS are released from an aminoacyl AMP-AARS complex once formed, and they are used again for forming the aminoacyl AMP-AARS complex, so that reaction products such as pyrophosphoric acid to be measured can be ultimately produced up to a molar number larger than that of the amino acids contained in the sample, and an amino acid quantification kit for performing the method.

Abstract: A random access memory includes a data signal line, a data-synchronization signal line for a data synchronization signal which provides a synchronization signal when data is transmitted to the data signal line, and a setting module. The setting module determines whether the data signal line is set to be a data signal line for common input/output use, a data signal line for output-only use, or a data signal line for input-only use, and further determines whether the data-synchronization signal line is set to be a data-synchronization signal line for common input/output use, a data-synchronization signal line for output-only use, or a data-synchronization signal line for input-only use.

Abstract: The present invention has an object of providing a high-speed, low-cost, and user-friendly information processing system that can ensure scalability of memory capacity. The information processing system is configured to include an information processing device, a volatile memory, and a nonvolatile memory. By serially connecting the information processing device, the volatile memory, and the nonvolatile memory and reducing the number of connection signals, processing speed is increased while maintaining the scalability of memory capacity. When transferring data of the nonvolatile memory to the volatile memory, error correction is performed, thereby improving reliability. The information processing system including the plurality of chips is configured as an information-processing system module in which the chips are alternately stacked and arranged, and wired by a ball grid array (BGA) or by bonding between the chips.

Abstract: The present invention has an object of providing a high-speed, low-cost, and user-friendly information processing system that can ensure scalability of memory capacity. The information processing system is configured to include an information processing device, a volatile memory, and a nonvolatile memory. By serially connecting the information processing device, the volatile memory, and the nonvolatile memory and reducing the number of connection signals, processing speed is increased while maintaining the scalability of memory capacity. When transferring data of the nonvolatile memory to the volatile memory, error correction is performed, thereby improving reliability. The information processing system including the plurality of chips is configured as an information-processing system module in which the chips are alternately stacked and arranged, and wired by a ball grid array (BGA) or by bonding between the chips.

Abstract: Provided is a device, including: a first terminal which receives an external clock signal; a clock generation circuit connected to the first terminal to generate an internal clock signal based on the external clock signal; word lines and bit lines; amplifier circuits connected to the bit lines, respectively; and a control unit. The control unit controls, in a test operation, at least one of the word lines to repeat a selected state and an unselected state in accordance with the internal clock signal during a first period, and maintains the amplifier circuits in an active state during the first period. The control unit further controls, in a normal operation, the amplifier circuits to switch between the active state and an inactive state depending on switching between the selected state and the unselected state of the at least one of the word lines.

Abstract: Provided is a device, including: a first terminal which receives an external clock signal; a clock generation circuit connected to the first terminal to generate an internal clock signal based on the external clock signal; word lines and bit lines; amplifier circuits connected to the bit lines, respectively; and a control unit. The control unit controls, in a test operation, at least one of the word lines to repeat a selected state and an unselected state in accordance with the internal clock signal during a first period, and maintains the amplifier circuits in an active state during the first period. The control unit further controls, in a normal operation, the amplifier circuits to switch between the active state and an inactive state depending on switching between the selected state and the unselected state of the at least one of the word lines.

Abstract: A semiconductor memory device includes data input/output terminals (DQ0 to DQ31), a memory cell array 122, and a data latch circuit 111 for temporarily latching data captured from the data input/output terminals and writing the data in the memory cell array with a delay in a normal write operation. The device also includes a test mode in which the data latch circuit latches data read to the data input/output terminals in a read operation and writes previously latched data in the memory cell array without newly latching data from the data input/output terminals in a write operation.

Abstract: A semiconductor memory device includes data input/output terminals (DQ0 to DQ31), a memory cell array 122, and a data latch circuit 111 for temporarily latching data captured from the data input/output terminals and writing the data in the memory cell array with a delay in a normal write operation. The device also includes a test mode in which the data latch circuit latches data read to the data input/output terminals in a read operation and writes previously latched data in the memory cell array without newly latching data from the data input/output terminals in a write operation.

Abstract: A semiconductor memory device includes data input/output terminals (DQ0 to DQ31), a memory cell array 122, and a data latch circuit 111 for temporarily latching data captured from the data input/output terminals and writing the data in the memory cell array with a delay in a normal write operation. The device also includes a test mode in which the data latch circuit latches data read to the data input/output terminals in a read operation and writes previously latched data in the memory cell array without newly latching data from the data input/output terminals in a write operation.

Abstract: Provided is a device, including: a first terminal which receives an external clock signal; a clock generation circuit connected to the first terminal to generate an internal clock signal based on the external clock signal; word lines and bit lines; amplifier circuits connected to the bit lines, respectively; and a control unit. The control unit controls, in a test operation, at least one of the word lines to repeat a selected state and an unselected state in accordance with the internal clock signal during a first period, and maintains the amplifier circuits in an active state during the first period. The control unit further controls, in a normal operation, the amplifier circuits to switch between the active state and an inactive state depending on switching between the selected state and the unselected state of the at least one of the word lines.

Abstract: In an information processing system, a plurality of information processing devices CHIP0 and CHIP1 are connected to multiport memory MPMEM0 that has a plurality of ports, and memory areas in multiport memory MPMEM0 can be altered to memory areas occupied by particular ports and memory areas shared by a plurality of ports. At such times, immediately after the occurrence of a request from a port, the status of this request may be supplied from other ports.

Abstract: A wireless base station includes: a trend factor regression expression calculator for determining, on the basis of measured wireless communication environment factor, the trend of the variation in the environment factor; a trend prediction value calculator for calculating, on the basis of the determined trend of the variation in the environment factor, the environment prediction value; an irregular variation factor calculator for calculating, on the basis of the difference between the determined trend of the environment factor variation and the measured environment factor, the magnitude of correction to be applied to the environment prediction value; and a radio environment prediction correction unit for correcting the environment prediction value according to the tolerance of the base station for its communication failure risk.

Abstract: A cellular mobile communication system, in which a plurality of base stations communicate with mobile stations, provides a retrieval unit, in which each base station retrieves the information regarding the radio communication status of each base station communicating with the predetermined mobile station, a decision unit, which makes a decision as to whether or not to permit interstation-cooperated communication with each base station based on the information, and a determination unit which determines the communication method adopted in the mobile station based on the decision result.

Abstract: In a method and a RS (Relay Station) for aggregating service connection identifiers in IEEE 802.16, the RS receives a 1st QoS (Quality of Service) from a 1st MS (Mobile subscriber Station), and stores a 1st SFID/CID (Service Flow Identifier)/CID (Connection Identifier) between a BS (Base Station)-RS corresponding to a 2nd SFID/CID between the RS-MS in table information. The RS receives a DSA-REQ (Dynamic Service Addition Request) including a QoS same as the 1st QoS from a 2nd MS, and sends a DSC-REQ (Dynamic Service Change REQuest) to the BS. Then, the RS receives a DSC-RSP (Dynamic Service Change ReSPonse) from the BS, assigns a 3rd SFID/CID between the RS-MS, and stores a 3rd SFID/CID corresponding to the 1st SFID/CID in the table information. The RS sends a DSA-RSP (Dynamic Service Addition ReSPonse) including 3rd SFID/CID to 2nd MS.

Abstract: To provide a first internal voltage generating circuit that generates an internal voltage based on a first external voltage and a second internal voltage generating circuit that generates the internal voltage based on a second external voltage. The semiconductor device generates an internal voltage from a plurality of the first and second external voltages. These external voltages can be utilized efficiently depending on a load state. Therefore, even in a semiconductor device with greatly varying consumption power, it is not necessary to enlarge only a particular power supply device.