Abstract: A desired automobile speed signal memory circuit for an automobile speed control system to maintain actual automobile speed constant at a desired speed. The memory circuit memorizes an actual automobile speed signal at the moment a desired speed set switch is closed. This memorized automobile speed signal is then used as a reference signal by the automobile speed control system to keep the actual automobile speed constant. The memory circuit has a capacitor which memorizes the desired speed signal, a first FET which forms a memorization loop with the capacitor upon the closure of the desired speed set switch, and a second FET which supplies the memorized desired speed signal on the capacitor in an impedance conversion mode as the reference signal used by the automobile speed control system to maintain constant the speed of the automobile.

Abstract: The idle speed of an engine is controlled in response to a control signal derived from the voltage across a thermistor responsive to the temperature of the engine cooling water. The thermistor voltage level varies exponentially with temperature changes. An engine idle speed control signal generator circuit includes a network of resistors, diodes and a transistor which produces an output control signal whose maximum level is limited to a value corresponding to a desired maximum idle speed, and whose minimum level is maintained above a value corresponding to the minimum desired idling speed. The circuit also adjusts the level of the output control signal to compensate for varying engine loads and faults in the circuit.

Abstract: In an electronic speed control circuit for automotive vehicles, a memory capacitor is connected at one end thereof to a speed signal generator and at the other end thereof to the gate of a field effect transistor to memorize a command speed signal. The electronic control circuit comprises a setting circuit for momentarily applying a constant voltage to a common junction between the gate of the field effect transistor and the memory capacitor. The setting circuit includes a second field effect transistor whose source is connected to a constant voltage circuit and whose drain is connected to the common junction between the memory capacitor and the first-named field effect transistor and a manual control circuit connected to the gate of the second field effect transistor to normally connect the gate of the second field effect transistor to the ground and to momentarily connect the constant voltage circuit to the gate of the second field effect transistor upon actuation of the manual control circuit.