Abstract: A clock handoff circuit outputting data in synchronism with a first clock input thereto as output data in synchronism with a second clock, includes: a dual port RAM capable of performing writing and reading independently of each other; a write address control section controlling write addresses of the dual port RAM in which the input data is written; a blank address detecting section detecting blank addresses among the write addresses in which the input data is not written; and a read address conversion section converting the write addresses of the dual port RAM excluding the blank address into read addresses from which the output data are read out.

Abstract: An image display apparatus includes an active-period interlaced-to-progressive (IP) converter configured to convert active periods (video periods) included in interlaced signals into progressive signals; a blanking-period IP converter configured to convert blanking periods included in the interlaced signals into progressive signals; a multiplexer configured to generate and output display data including both the progressive signals associated with the active periods and the progressive signals associated with the blanking periods; and a display unit configured to display the data output from the multiplexer. The blanking-period IP converter is configured to generate the progressive signals associated with the blanking periods by executing IP conversion in which values copied from data included in the interlaced signals or values corresponding to black pixels are set as pixel values of an interpolated field not included in field data of the interlaced signals.

Abstract: A clock handoff circuit outputting data in synchronism with a first clock input thereto as output data in synchronism with a second clock, includes: a dual port RAM capable of performing writing and reading independently of each other; a write address control section controlling write addresses of the dual port RAM in which the input data is written; a blank address detecting section detecting blank addresses among the write addresses in which the input data is not written; and a read address conversion section converting the write addresses of the dual port RAM excluding the blank address into read addresses from which the output data are read out.

Abstract: A signal processing circuit includes: a memory storing an image signal; a write control unit generating a write control signal in synchronization with the input image signal and frame identification information, and storing the input image signal in the memory so that the input image signal corresponds to the frame identification information on the basis of the write control signal; and a read control unit generating a read control signal through obtaining a vertical synchronization signal supplied from outside based on a timing signal of an output horizontal frequency, and reading an image signal that corresponds to the frame identification information from the memory on the basis of the read control signal and the frame identification information supplied from outside.

Abstract: A video signal processing apparatus includes a video signal synthesis section for, when positions after and before a border position by a predetermined length are respectively set as first and second positions, taking out a first main area part corresponding to a part before the border position and a first border area part corresponding to a part from the border position to the first position from a first video signal and also a second border area part corresponding to a part from the second position to the border position and a second main area part corresponding to a part after the border position from a second video signal for synthesis, an image processing section for performing an image processing on the synthesized video signal, and a video signal output section for removing the first and second border area parts from the synthesized video signal to obtain an output video signal.

Abstract: An image display apparatus includes an interlaced-to-progressive converter configured to receive input of interlaced signals and to convert the interlaced signals into progressive signals including interpolated pixels generated by interpolation; a level converter configured to adjust output levels of the interpolated pixels included in the progressive signals generated by the interlaced-to-progressive converter; and a display unit employing a frame-holding display method, configured to output an image obtained through the level conversion by the level converter.

Abstract: An image display apparatus includes the following elements. An IP converter performs signal conversion processing for converting an interlace signal into a progressive signal including information on interpolated pixels. A frame controller temporally divides an input image frame to generate a plurality of sub-frames. A high-frequency-enhanced sub-frame generator and a high-frequency-suppressed sub-frame generator perform filtering processing on the sub-frames to generate high-frequency-enhanced sub-frames and high-frequency-suppressed sub-frames, respectively. A first output controller alternately outputs the high-frequency-enhanced sub-frames and the high-frequency-suppressed sub-frames. A gain controller adjusts an output level of the sub-frames.

Abstract: An image display apparatus includes a display unit including a liquid crystal panel; a video signal processor configured to perform signal processing on the basis of an image display form in the display unit; and an AC drive controller configured to control video display by receiving a result of the signal processing performed in the video signal processor and controlling a voltage applied to the liquid crystal panel included in the display unit. The AC drive controller performs, for each pixel of the liquid crystal panel, AC drive control of alternately switching a polarity between + and ? in units of pairs of the same signal processing, each pair being two pixels on time series on which signal processing of the same category is performed in the video signal processor.

Abstract: A video signal processing apparatus includes a video signal synthesis section for, when positions after and before a border position by a predetermined length are respectively set as first and second positions, taking out a first main area part corresponding to a part before the border position and a first border area part corresponding to a part from the border position to the first position from a first video signal and also a second border area part corresponding to a part from the second position to the border position and a second main area part corresponding to a part after the border position from a second video signal for synthesis, an image processing section for performing an image processing on the synthesized video signal, and a video signal output section for removing the first and second border area parts from the synthesized video signal to obtain an output video signal.

Abstract: An image display apparatus includes an active-period interlaced-to-progressive (IP) converter configured to convert active periods (video periods) included in interlaced signals into progressive signals; a blanking-period IP converter configured to convert blanking periods included in the interlaced signals into progressive signals; a multiplexer configured to generate and output display data including both the progressive signals associated with the active periods and the progressive signals associated with the blanking periods; and a display unit configured to display the data output from the multiplexer. The blanking-period IP converter is configured to generate the progressive signals associated with the blanking periods by executing IP conversion in which values copied from data included in the interlaced signals or values corresponding to black pixels are set as pixel values of an interpolated field not included in field data of the interlaced signals.

Abstract: An image display apparatus includes an interlaced-to-progressive converter configured to receive input of interlaced signals and to convert the interlaced signals into progressive signals including interpolated pixels generated by interpolation; a level converter configured to adjust output levels of the interpolated pixels included in the progressive signals generated by the interlaced-to-progressive converter; and a display unit employing a frame-holding display method, configured to output an image obtained through the level conversion by the level converter.

Abstract: An image display apparatus includes the following elements. An IP converter performs signal conversion processing for converting an interlace signal into a progressive signal including information on interpolated pixels. A frame controller temporally divides an input image frame to generate a plurality of sub-frames. A high-frequency-enhanced sub-frame generator and a high-frequency-suppressed sub-frame generator perform filtering processing on the sub-frames to generate high-frequency-enhanced sub-frames and high-frequency-suppressed sub-frames, respectively. A first output controller alternately outputs the high-frequency-enhanced sub-frames and the high-frequency-suppressed sub-frames. A gain controller adjusts an output level of the sub-frames.

Abstract: An image display apparatus includes a display unit including a liquid crystal panel; a video signal processor configured to perform signal processing on the basis of an image display form in the display unit; and an AC drive controller configured to control video display by receiving a result of the signal processing performed in the video signal processor and controlling a voltage applied to the liquid crystal panel included in the display unit. The AC drive controller performs, for each pixel of the liquid crystal panel, AC drive control of alternately switching a polarity between + and ? in units of pairs of the same signal processing, each pair being two pixels on time series on which signal processing of the same category is performed in the video signal processor.

Abstract: In a data recording method and a data recording apparatus relating to the present invention, ECC blocks using 36 product codes are recorded on 12 tracks through scanning operations performed three times. First of all, first sync-blocks each constituted by adding a C1 parity to the data string of video data constituting an internal encoding calculation data stream are sequentially recorded. When the first sync-blocks are completely recorded, second sync-blocks each constituted by adding the C1 parity to the data string of C2 parity constituting the internal encoding calculation data stream are sequentially recorded. By recording the C2 parity at one time in a later stage, the system delay can be minimized.

Abstract: In a data recording method and a data recording apparatus relating to the present invention, ECC blocks using 36 product codes are recorded on 12 tracks through scanning operations performed three times. First of all, first sync-blocks each constituted by adding a C1 parity to the data string of video data constituting an internal encoding calculation data stream are sequentially recorded. When the first sync-blocks are completely recorded, second sync-blocks each constituted by adding the C1 parity to the data string of C2 parity constituting the internal encoding calculation data stream are sequentially recorded. By recording the C2 parity at one time in a later stage, the system delay can be minimized.

Abstract: Input terminals to which two types of serial data with similar formats are sent are disposed. Video data sent to the normal dubbing input terminal is data that has not been compressed/encoded. Data sent to the straight dubbing input terminal is data that has been compressed and encoded. Data received from the input terminal includes a sync error flag (error flag for each sync block) that is OR output data of data added by a reproducing VTR and transmission error information. The sync error flag is sent to an ECC encoder through a format converter not through an BRR encoder. An output signal of an ECC encoder is recorded to a magnetic tape by recording heads through a recording driver.

Abstract: A line number LN is extracted from serial data corresponding to BTA S-004 standard. The line number LN is placed as LN0 and LN1 to each of a luminance signal Y and color difference signals Pr/Pb of a 4:2:2 signal. The 4:2:2 signal is converted into a 3:1:1 signal by a bandwidth-compressing means. In addition, the 3:1:1 signal is re-arranged to two-channel signals Ch0 and Ch1 with the same format at a transmission rate of 46.40625 MHz. Thereafter, the, signals are processed at the transmission rate of 46.40625. The line number LN is placed as LN0 and LN1 at the beginning of one horizontal interval.

Abstract: Input terminals to which two types of serial data with similar formats are sent are disposed. Video data sent to the input terminal is data that has not been compressed/encoded. Data sent to the straight dubbing input terminal is data that has been compressed and encoded. Data received from the input terminal includes a sync error flag (error flag for each sync block) that is OR output data of data added by a reproducing VTR and transmission error information. The sync error flag is sent to an ECC encoder through a format converter not through an BRR encoder. An output signal of an ECC encoder is recorded to a magnetic tape by recording heads through a recording driver.

Abstract: A Reed Solomon error correction code calculator is disclosed, that comprises a plurality of modules, each of which has a memory, a matrix calculator, and an exclusive-OR circuit, the plurality of modules being cascade connected, and at least one register disposed between each of the plurality of modules.

Abstract: A digital video signal of one frame is recorded as diagonal tracks on a magnetic tape by four recording heads. One frame is recorded as six segments (twelve tracks). Adjacent tracks is reverse azimuths. In each track of even segments, an auxiliary data sync block is recorded at the last position of a video sector v1. In each track of odd segments, an auxiliary data sync block is recorded at the beginning position of a video sector v1. Since an auxiliary data sync block is recorded at spaced positions on a tape, it can be prevented that an auxiliary data cannot be read at all on a tape scrached in the longitudinal direction.