Abstract: It is one object of the present invention to provide a steering device for a vehicle improving a resolution of detecting a steering reaction force thereby to control precisely a reaction actuator and to improve a steering feeling. The steering device for the vehicle is equipped with a reaction actuator 19 acting a steering reaction force on a steering wheel 1. This device further includes a steering angle sensor 11 detecting a steering angle ?h of the steering wheel 1, a controller 20 controlling the reaction actuator 19 according to the steering angle ?h, a torque sensor 12 detecting a steering torque Th acted on the steering wheel 1. The controller 20 controls in a feedback way the reaction actuator 11 based on the steering torque Th in a predetermined range including a middle point of the steering angle. The controller 20 drives, in a open-loop way without feed-backing the steering torque Th, the reaction actuator 19 out of the predetermined range of the steering angle ?h.

Abstract: A semiconductor device has a plurality of fuse element portions each of which including a first fuse interconnect having a fuse to be portion, a second fuse interconnect connected to an internal circuit, a first impurity diffusion layer for electrically connecting the first fuse interconnect and the second fuse interconnect, and a second impurity diffusion layers. The first fuse interconnect, the second fuse interconnect, and the first impurity diffusion layer of each of the plurality of fuse element portions are arranged approximately parallel to one another at a predetermined pitch distance.

Abstract: It is one object of the present invention to provide a steering device for a vehicle improving a resolution of detecting a steering reaction force thereby to control precisely a reaction actuator and to improve a steering feeling. The steering device for the vehicle is equipped with a reaction actuator 19 acting a steering reaction force on a steering wheel 1. This device further includes a steering angle sensor 11 detecting a steering angle ?h of the steering wheel 1, a controller 20 controlling the reaction actuator 19 according to the steering angle ?h, a torque sensor 12 detecting a steering torque Th acted on the steering wheel 1. The controller 20 controls in a feedback way the reaction actuator 11 based on the steering torque Th in a predetermined range including a middle point of the steering angle. The controller 20 drives, in a open-loop way without feed-backing the steering torque Th, the reaction actuator 19 out of the predetermined range of the steering angle ?h.

Abstract: A semiconductor device has a plurality of fuse element portions each of which including a first fuse interconnect having a fuse to be portion, a second fuse interconnect connected to an internal circuit, a first impurity diffusion layer for electrically connecting the first fuse interconnect and the second fuse interconnect, and a second impurity diffusion layers. The first fuse interconnect, the second fuse interconnect, and the first impurity diffusion layer of each of the plurality of fuse element portions are arranged approximately parallel to one another at a predetermined pitch distance.

Abstract: The present invention relates to a method of manufacturing a semiconductor device; which comprises the steps of: forming an interlayer insulating film on a semiconductor substrate having a gate electrode, a dopant diffusion layer and a silicide layer which is set on said dopant diffusion layer; forming an opening in said interlayer insulating film which is laid on said dopant diffusion layer in such a way that said silicide layer may not be exposed; forming, in a region inclusive of internal lateral faces of said opening, an insulating film for sidewall at or above 700° C. by the CVD; and performing an etch back and thereby forming, on the internal lateral face of said opening, a sidewall made of said insulating film for sidewall.

Abstract: A non-volatile semiconductor memory device is constituted by a plurality of thin film memory transistors, each having a control gate electrode formed on an insulating film on a semiconductor substrate, a first gate insulating film covering said control gate electrode, a floating gate electrode formed on said first gate insulating film, a second gate insulating film provided on said floating gate electrode, a channel region of a first conductivity type semiconductor film provided on said second gate insulating film, and source/drain regions of a second conductivity type semiconductor film formed with said channel region being interposed therebetween. A memory device such as an EPROM or FEPROM is formed by using the above thin film memory transistors. The invention provides a semiconductor memory device which operates at a high speed and in which it is possible to achieve a high integration.

Abstract: A mask programmable read only memory device comprises a plurality of memory cell blocks each having a plurality of first series combinations of memory transistors and a plurality of second series combinations of memory transistors, and each of the memory transistors is operative in either enhancement or depletion mode, wherein the plurality of first series combinations are respectively overlapped with the plurality of second series combinations so as to share word lines therebetween, thereby increasing the integration density without sacrifice of the real estate.

Abstract: A electrically erasable and programmable read only memory device has a memory cell array implemented by a plurality of floating gate type memory transistors, and each of the floating gate type memory transistors is implemented by a thin film field effect transistor with a floating gate electrode formed on a relatively thick insulating film covering a major surface of a semiconductor substrate so that the biasing conditions and crystal defects do not have any influence on the floating gate type memory transistor.

Abstract: An electrically erasable and programmable read only memory device includes a plurality of series combinations of memory cells arranged in rows and columns, bit lines, a plurality of word lines, and a source line. Each bit line of the plurality of bit lines is respectively coupled to a front memory cell of the series combinations in one of the columns. The source line is coupled to rearmost memory cells of the plurality of series combinations of each of the columns. Each of the word lines is respectively coupled to each row of the memory cells. Each of the memory cells is implemented by a parallel combination of a floating gate field effect transistor coupled to a first word line and a switching transistor coupled to a second word line. The device is capable of performing selective write operations and simultaneously erasing the series combination of memory cells. The floating gate field effect transistors are formed on a major surface of a semiconductor substrate.

Abstract: An electrically erasable and programmable read only memory device comprises a plurality of series combinations of memory cells arranged in rows and columns, bit lines each coupled to the front memory cells of the series combinations in one of the columns, a source line coupled to the rearmost memory cells of the plurality of series combinations, and word lines associated with the row of the memory cells, wherein each of the memory cells is implemented by a parallel combination of a floating gate type memory transistor and a switching transistor coupled to first and second word lines, respectively, so that any memory cell is rewriteable without simultaneous erasing operation on the series combination.

Abstract: A PTC heating element with a honeycomb ceramic body comprising a barium titanate and semiconductor element, which provides the ceramic body with a positive temperature coefficient of resistance over the Curie point. An electrode is deposited on each end of the honeycomb body. The electrodes according to the present invention have a non-ohmic property, while the conventional electrodes have been ohmic. A high rush current and migration are advantageously decreased by the non-ohmic electrodes.

Abstract: An erasable, programmable read-only memory device comprises a plurality of memory cells of channel injection type. First and second impurity regions used as source and drain have different configurations such that when the same level of voltages are applied to first and second impurity regions, respectively, the intensity of electric field near the channel region in the depletion layer between the second impurity region and the substrate is weaker than that in the depletion layer between the first impurity region and the substrate. In the writing operation, a higher voltage in absolute value is applied to the first impurity region and channel current flows in one direction. Therefore, hot electrons can be effectively injected into the floating gate near the first impurity region. On the other hand in the reading operation, a higher voltage in absolute value is applied to the second impurity region and channel current flows in the opposite direction.