Patents by Inventor Shoji Mimotogi
Shoji Mimotogi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20040123267Abstract: Setting values of a light exposure and a focus position are set in an exposure process for forming a pattern on a substrate. Pseudo measured dimensions of the pattern are calculated with respect to each of the combinations of the setting values. ED-trees and a plurality of margin curves are calculated based on the pseudo measured dimensions with respect to each of the combinations. A dispersion of a tolerance of the light exposure of the margin curves is calculated at a depth of focus corresponding to a maximum difference in height of the substrate.Type: ApplicationFiled: September 30, 2003Publication date: June 24, 2004Inventor: Shoji Mimotogi
-
Patent number: 6649310Abstract: A method of manufacturing a photomask includes determining an average value of dimensions of a pattern in a photomask. determining an in-plane uniformity of the dimensions, determining an exposure latitude on the basis of the average value and the in-plane uniformity. The exposure latitude depends on dimensional accuracy of the pattern.Type: GrantFiled: August 29, 2001Date of Patent: November 18, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Masamitsu Itoh, Shigeki Nojima, Shoji Mimotogi, Osamu Ikenaga
-
Patent number: 6632592Abstract: A resist pattern forming method of forming a pattern on a resist film formed on a wafer by using a projection exposure apparatus generates a resized pattern of an active area and its inverted pattern, then generates a logical product pattern of a gate pattern to be exposed and the resized pattern, generates a first mask having a logical sum pattern of the inverted pattern and the logical product pattern as a light shielding film, generates a second mask having a logical sum pattern of the resized pattern and the gate pattern as a light shielding film, exposes the resist film on the wafer using the first mask under a condition that an numerical aperture of the projection exposure apparatus is small, and then exposes the resist film on the wafer using the second mask under a condition that the numerical aperture of the projection exposure apparatus is large.Type: GrantFiled: September 7, 2000Date of Patent: October 14, 2003Assignee: Kabushiki Kaisha ToshibaInventor: Shoji Mimotogi
-
Publication number: 20030117627Abstract: There is here disclosed a method for inspecting an exposure apparatus, comprising illuminating a mask, in which a mask-pattern including at least a set of a first mask-pattern and a second mask-pattern mutually different in shape is formed, from a direction in which a point located off an optical axis of an exposure apparatus is a center of illumination, and exposing and projecting an image of the mask-pattern toward an image-receiving element, and measuring a mutual relative distance between images of the first and second mask-patterns exposed and projected on the image-receiving element, thereby inspecting a state of an optical system of the exposure apparatus.Type: ApplicationFiled: November 5, 2002Publication date: June 26, 2003Inventors: Takashi Sato, Shoji Mimotogi, Takahiro Ikeda, Soichi Inoue
-
Patent number: 6418553Abstract: There are provided a circuit designing method using a half-tone phase shift mask for forming a circuit pattern on a semiconductor substrate, and a computer-readable medium having recorded a program for causing a computer to execute the circuit designing method.Type: GrantFiled: March 10, 2000Date of Patent: July 9, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Akiko Yamada, Koji Hashimoto, Shoji Mimotogi
-
Publication number: 20020025480Abstract: A method of manufacturing a photomask comprises determining an average value and an in-plane uniformity in a dimension of a pattern of the photomask, determining an exposure latitude as the photomask is employed on the basis of the average value and the in-plane uniformity in the dimension of the pattern, and judging if the photomask is defective or non-defective on the basis of whether or not the exposure latitude is determined satisfy a prescribed exposure latitude.Type: ApplicationFiled: August 29, 2001Publication date: February 28, 2002Inventors: Masamitsu Itoh, Shigeki Nojima, Shoji Mimotogi, Osamu Ikenaga
-
Patent number: 6294297Abstract: A process tolerance calculating method which, in order to obtain a process tolerance in a process for forming a pattern on an object, to be processed, with the use of a projection light exposure apparatus, calculates a process tolerance for finding a relation of a light exposure amount and focal point position corresponding to a finished pattern of an allowable dimension value, comprising the steps of: (1) measuring a variation in dimension of a to-be-formed pattern in terms of its length by varying a light exposure amount and focal point position by the projecting light exposure apparatus; (2) finding a dependence of the measured pattern dimension upon the light exposure amount, at each varying focal position through a curve approximation; (3) finding a dependence of the pattern dimension which is found through the curve approximation upon the focal point position at each varying light exposure amount; (4) finding a light exposure amount corresponding to a finished pattern of an allowable dimension valueType: GrantFiled: February 23, 1999Date of Patent: September 25, 2001Assignee: Kabushiki Kaisha ToshibaInventor: Shoji Mimotogi
-
Patent number: 6252651Abstract: An exposure method includes the phase-shifting mask supply step, the phase-shifting mask being prepared by selectively forming a light-shielding portion and a phase shifter on a substrate, and the resist exposure step of performing both exposure of a resist by dark field illumination light and exposure of the resist by bright field illumination light by using the phase-shifting mask, thereby removing residual resist generated by the influence of the edge of the phase shifter.Type: GrantFiled: November 10, 1999Date of Patent: June 26, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Tadahito Fujisawa, Satoshi Tanaka, Akiko Mimotogi, Shoji Mimotogi, Soichi Inoue
-
Patent number: 6249900Abstract: In a method of designing an LSI pattern, before pattern designing, the length B and line width W of a rectangle obtained by dividing a bent design pattern are used as parameters. A line width C at which a desired line width W is obtained for the length B of the rectangle is determined to be a correction value. Each correction value is listed in a table. In designing a pattern, the upper limit Bmax of the length of a line segment is first determined. Of the line segments of the bent design pattern, a shorter one than the upper limit Bmax is extracted. Then, a rectangle including the extracted line segment is extracted. Thereafter, the line width W of the extracted rectangle is corrected to the line width C by reference to the table.Type: GrantFiled: October 21, 1998Date of Patent: June 19, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Toshiya Kotani, Shoji Mimotogi, Soichi Inoue, Kazuko Yamamoto
-
Patent number: 6225033Abstract: An anti-reflection film has been formed on an SiO2 film on a silicon substrate formed on a silicon wafer. A chemical amplification positive resist is formed on the anti-reflection film. The resist is exposed to light. Vapor of strong alkali is applied to a surface of the chemical amplification positive resist. The entire resist is developed with a developing solution, thereby forming a resist pattern.Type: GrantFiled: October 6, 1999Date of Patent: May 1, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Yasunobu Onishi, Kentaro Matsunaga, Shoji Mimotogi, Katsuya Okumura
-
Patent number: 6107013Abstract: An exposure method includes the phase-shifting mask supply step, the phase-shifting mask being prepared by selectively forming a light-shielding portion and a phase shifter on a substrate, and the resist exposure step of performing both exposure of a resist by dark field illumination light and exposure of the resist by bright field illumination light by using the phase-shifting mask, thereby removing residual resist generated by the influence of the edge of the phase shifter.Type: GrantFiled: December 12, 1997Date of Patent: August 22, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Tadahito Fujisawa, Satoshi Tanaka, Akiko Mimotogi, Shoji Mimotogi, Soichi Inoue
-
Patent number: 6045981Abstract: A method of manufacturing a semiconductor device, which comprises the steps of, selectively silylating a photosensitive resin film by exposing the photosensitive resin film according to an exposure pattern thereby to form a silylated portion having a glass transition temperature which is lower than that of the photosensitive resin film and at the same time exposing the photosensitive resin film to an intermediate temperature between the glass transition temperature of the silylated portion and the glass transition temperature of the photosensitive resin film thereby fluidizing the silylated portion so as to cover a portion of the photosensitive resin film neighboring the silylated portion with the fluidized silylated portion, and developing the photosensitive resin film by making use of the silylated portion and the portion of photosensitive resin film covered by the fluidized silylated portion as a mask.Type: GrantFiled: February 6, 1998Date of Patent: April 4, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Kentaro Matsunaga, Akiko Mimotogi, Shoji Mimotogi, Soichi Inoue
-
Patent number: 5906903Abstract: A process tolerance calculating method which, in order to obtain a process tolerance in a process for forming a pattern on an object, to be processed, with the use of a projection light exposure apparatus, calculates a process tolerance for finding a relation of a light exposure amount and focal point position corresponding to a finished pattern of an allowable dimension value, comprising the steps of:(1) measuring a variation in dimension of a to-be-formed pattern in terms of its length by varying a light exposure amount and focal point position by the projecting light exposure apparatus;(2) finding a dependence of the measured pattern dimension upon the light exposure amount, at each varying focal position through a curve approximation;(3) finding a dependence of the pattern dimension which is found through the curve approximation upon the focal point position at each varying light exposure amount;(4) finding a light exposure amount corresponding to a finished pattern of an allowable dimension value, at eacType: GrantFiled: January 6, 1998Date of Patent: May 25, 1999Assignee: Kabushiki Kaisha ToshibaInventor: Shoji Mimotogi
-
Patent number: 5889686Abstract: A profile of a developed resist is exactly simulated irrespective of whether or not a resist pattern is dense. A dissolution rate of a film to be processed, which film is provided on a substrate, is varied in accordance with a concentration of a developer and the profile of the developed resist is simulated with use of the varied dissolution rate. In addition, a spatial average of an optical image of a resist, which is averaged in the thickness direction of the resist, is calculated and the dissolution rate of the resist is modulated by using the calculated spatial average. The profile of the resist is simulated by using the modulated dissolution rate. Therefore, the profile of the resist on the substrate, which profile varies when the resist is exposed in a desired pattern and developed, can be exactly estimated.Type: GrantFiled: April 22, 1997Date of Patent: March 30, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Shoji Mimotogi, Soichi Inoue
-
Patent number: 5889678Abstract: In a topography simulation method, the topography of a resist pattern after curing treatment can be precisely estimated without producing a complex physical model or performing parameter measurement. Specifically, in the method of estimating the topography of a resist pattern, which is formed by selectively removing a part of a resist provided on a substrate and contracts due to curing treatment, the resist pattern is divided into a plurality of cells and the cells are contracted in accordance with a volume shrinkage amount per unit volume of the resist in the curing treatment. Then, the cells located closer to an interface between the substrate and the resist pattern are flattened to a higher degree in parallel to the substrate, and the deformed cells are brought together toward a shrinkage reference line passing through a center of a line pattern and toward the substrate.Type: GrantFiled: May 12, 1997Date of Patent: March 30, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Soichi Inoue, Satoshi Tanaka, Shoji Mimotogi, Yasunobu Onishi
-
Patent number: 5876885Abstract: The profile simulation method of predicting a processed profile of a surface of a substrate to be changed by physically or chemically processing a film on the substrate to be processed comprises a step of changing a processing speed in correspondence with a convex portion and a recessed portion of the film on the substrate.Type: GrantFiled: July 25, 1996Date of Patent: March 2, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Shoji Mimotogi, Soichi Inoue, Akiko Mimotogi
-
Patent number: 5745388Abstract: A profile simulation method of predicting a profile of a surface of a film to be processed which changes when the surface of the film on a substrate is physically or chemically processed, is characterized by comprising the steps of setting a plurality of representative points on the surface of the film before a process, moving the plurality of representative points in a first direction perpendicular to the surface of the film on the substrate in accordance with processing velocities at the plurality of representative points, switching the moving direction of the representative points from the first direction to a second direction parallel to the surface of the film on the substrate, and moving the plurality of representative points in the second direction in accordance with processing velocities at the plurality of representative points, and setting all loci of the plurality of representative points, which have moved from the first direction to the second direction in a predetermined processing time, as pathsType: GrantFiled: November 7, 1995Date of Patent: April 28, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Shoji Mimotogi, Soichi Inoue
-
Patent number: 5733687Abstract: When a pattern to be exposed onto a wafer is a periodic pattern, a periodic mask pattern substantially twice as large as the pattern to be exposed in the wafer is formed on a photomask by means of light transmission portions and halftone portions. The halftone portions are formed such that a phase difference between exposure light transmitted through the light transmission portions and exposure light transmitted through the halftone portions is set to be substantially 180.degree.. Moreover, in order to eliminate zeroth order diffraction light, amplitude transmittance t of the halftone portion is set to t.apprxeq.A1/A2 wherein A1 is an area of the halftone portion and A2 is an area of the light transmission portion. Further, amplitude transmittance t of the halftone portion is changed, and an amount of exposure light to the photomask is controlled, so that L&S patterns and isolated patterns are simultaneously transferred onto the wafer by one photomask.Type: GrantFiled: September 29, 1995Date of Patent: March 31, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Tanaka, Shoji Mimotogi, Tadahito Fujisawa, Soichi Inoue