Abstract: In order to inhibit forming cracks under a pad opening during ball bonding without increasing a chip size, a protective film includes a pad opening that exposes a part of a topmost layer metal film of the chip. A second metal film provided under the pad opening has a ring shape that defines a rectangular opening under the pad opening. The opening edge of the opening in the second metal film extends inwardly beyond the edge of the overlying pad opening. Vias connect the second metal film and the topmost layer metal film, and all of these vias are located outside the pad opening in plan view.

Abstract: In order to inhibit forming cracks under a pad opening during ball bonding without increasing a chip size, a protective film includes a pad opening that exposes a part of a topmost layer metal film. A second metal film provided under the pad opening has a ring shape that defines a rectangular opening under the pad opening. The opening edge of the opening in the second metal film extends inwardly beyond the edge of the overlying pad opening.

Abstract: A semiconductor device has a semiconductor substrate provided with a scribe region and an IC region. A first insulating film is disposed on the semiconductor substrate across the scribe region and the IC region. At least one separation groove is provided in the first insulating film in the scribe region. Side walls made of a plug metal film are formed only on respective lateral walls of the separation groove so that the plug metal film on the lateral walls does not extend out of the separation groove and does not exist on an upper surface of the first insulating film. A second insulating film covers at least the side walls formed on the respective lateral walls of the separation groove so that the side walls are disposed under the second insulating film.

Abstract: In order to inhibit a crack under a pad opening without increasing a chip size, a protective film (6) includes a pad opening (9) that exposes a part of a topmost layer metal film (3). The pad opening (9) is rectangular and square, and has an opening width of d0. A second metal film (2) has an opening under the pad opening (9). The opening is rectangular and square, and has an opening width of d4. A distance between an opening edge of the protective film (6) and an opening edge of the second metal film (2) is d3. The second metal film (2) has a rectangular donut shape, and protrudes to an inner side of the pad opening (9) by the distance d3.

Abstract: Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer.

Abstract: Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer.

Abstract: Provided is a semiconductor device suitable for preventing film peeling due to dicing and preventing abnormal discharge. The semiconductor device includes a scribe region (003) and an IC region (004). At least one separation groove (007) is provide in an inter-layer insulating film (002) in the scribe region 003, and a side wall (011) made of a plug metal film is formed on each lateral wall of the separation groove (007). A passivation film is provided to cover at least the side walls (011).

Abstract: Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer.

Abstract: A floating non-volatile memory has a substrate and source and drain regions disposed in a surface region of the substrate and spaced apart from each other with a channel forming semiconductor region disposed therebetween. A gate insulating film is disposed on the channel forming semiconductor region. A single crystal control region is disposed in the surface region of the substrate and is electrically separated from the channel forming semiconductor region. A control gate insulating film is disposed on the single crystal control region. A floating gate is disposed on the control gate insulating film and is capacitively coupled with the single crystal control region. A chemical-vapor-deposited shield insulating film is formed in a gas atmosphere charge-balanced on the floating gate. A shield conductive film is disposed on the chemical-vapor-deposited shield insulating film and capacitively coupled with the floating gate.

Abstract: Printing unevenness caused in forming a polarizing film by printing an ink liquid having a dichromatic dye is minimized to provide satisfactory LCD display characteristics. Bearings are erected on opposite sides of a table and are formed with vertical slots, into which the opposite ends of an axle of a printing cylinder are dropped, whereby the axle of the printing cylinder is loosely fitted in the right and left bearings. The bearings are horizontally movably constructed and connected to a horizontal motion drive (not shown). Further, right and left weights of equal heaviness are attached to the opposite sides of the axle of the printing cylinder. In producing a polarizing film, a substrate is placed on the table and a format having a number of fine grooves is attached to the printing cylinder and placed on the substrate. Ink liquid having a dichromatic dye is applied to the format to form a thin film of ink liquid on the format surface, and the bearings are horizontally moved along the printing direction.

Abstract: In a non-volatile memory in which a floating gate is provided above a single crystal control region, a potential of wiring, which is arranged above the floating gate, has a capacitive coupling with respect to the floating gate, or even one part in and on an insulating film on the floating gate is included or attached with electric charge, thereby varying the gate threshold voltage of the floating gate non-volatile memory measured from the single crystal control region. In order to solve the above-described problems, the present invention provides following methods. A shield conductive film is provided above a floating gate through a shield insulating film.

Abstract: To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.

Abstract: To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.

Abstract: A liquid crystal display includes an insulating substrate, a first metal layer formed on the substrate, a first insulating layer including an oxide of tantalum nitride with high ratio of nitrization formed on the first metal layer, a second insulating layer including an oxide of tantalum nitride with low ratio of nitrization formed on the first insulating layer, and a second metal layer formed on the second insulating layer.

Abstract: A chiral nematic type liquid crystal display device in which the twist angle of a torsional structure of a liquid crystal layer is as large as 180.degree. to 360.degree. and the birefringence of liquid crystal molecules is utilized. This liquid crystal display device is characterized in that: a liquid crystal layer is disposed between opposed substrates and orientation films formed of straight chain polymer having fluoro-alkyl side chain C.sub.n H.sub.m F.sub.2n+1-m (n being a natural number and m being a natural number of 0 or 2n or less) are provided on the respective inner surfaces of said substrates facing the liquid crystal layer.

Abstract: In a MOS transistor or memory cell that uses a thin oxide film as a gate insulation film, ion-implantation-induced damage protection films (mask oxide films) are formed on side walls of a polysilicon gate electrode to minimize flaws in the structure of the thin oxide film right under the polysilicon gate electrode edge, which are induced by the ion implantation performed during the process of forming self-aligned source and drain regions.

Abstract: A method of concurrently forming thick and thin field silicon oxide films for use as element separation on the silicon substrate. An under-layer silicon oxide film is formed over the silicon substrate. A silicon nitride film is chemically-vapor-deposited over the under-layer silicon oxide film. The silicon nitride film is selectively etched to expose the under-layer silicon oxide film to thereby form openings. The silicon substrate is annealed within a heated atmosphere of ammonia gas to convert a surface portion of the exposed under-layer silicon oxide film into a thermally nitrified silicon oxide film within the openings. The thermally nitrified silicon oxide film is selectively removed from some of the openings and maintained in the other openings. The silicon substrate is thermally oxidized through the openings to concurrently form relatively thick field oxide film within said some of the openings and relatively thin field oxide film within the other openings.