Abstract: There is provided a technique that includes: (a) performing: (a1) exciting a first oxidizing agent and a first reducing agent into a plasma state and supplying the first oxidizing agent and the first reducing agent thus excited to a substrate, which includes a first surface and a second surface; and (a2) exciting a second reducing agent into a plasma state and supplying the second reducing agent thus excited to the substrate; and (b) heat-treating the substrate subjected to (a).

Abstract: A vector data processing apparatus having a set of vector registers, one or more memory access pipelines, and one or more composite calculation pipelines, wherein the vector registers consist of a plurality of banks, and each bank is independently accessible. Each of the pipelines can cyclically access each of the banks of the vector registers when one or more of a predetermined number of time slots, through each of which time slots the access is carried out, are assigned to an instruction using the pipeline. Immediately when a memory access instruction is received, a vector unit control circuit, which controls operations of the vector data processing apparatus, assigns a time slot for a newly-detected memory access instruction using a memory access pipeline, if it is determined that the memory access pipeline is available based on the pipeline operation status flags, and that the time slot is available based on the detected status of the predetermined number of time slots.

Abstract: A multiprocessor control system which has at least one main storage unit, a plurality of main storage control units, a plurality of processing units, and a control bus. Each processing unit is connected to the main storage unit through one of the main storage control units. When each processing unit transmits a request for access to at least one main storage unit, the processing units transmit the request to the main storage control units to which each processing unit is connected, and simultaneously, to all of the other main storage control units, through the control bus. All of the main storage control units process the request from the processing unit, synchronously, and execute a busy check control or the like. Data transmitted between each processing unit and an arbitrary one of the main storage units is transmitted only through the main storage control unit to which the processing unit is connected.

Abstract: Population counting is performed by using a multiplying unit, in the computer system, including a plurality of multiplying sub-units for simultaneously executing partial multiplication among elements obtained by dividing a multiplicand data and a multiplier data in a regular multiplication mode. In a population counting mode, an input data for the population counting is divided into population counting elements instead of the multiplier data and population counting on the population counting elements are performed simultaneously using the multiplying sub-units which produce partial counted data of the population counting elements, and the partial counted data is sent to a carry save adder and a carry propagate adder by which a population counting result for the input data is obtained and output.

Abstract: An improved vector processor for processing a modified recurrent equation: a.sub.i =a.sub.i-2 .times.b.sub.i-1 .times.b.sub.i +b.sub.i .times.c.sub.i-1 +c.sub.i, where i is an integer: i=1, 2, 3, . . . , n, at a high speed. The vector processor includes a data distribution circuit (40a, 40b), at least one odd term calculation circuit (10A, 10AA), and at least one even term calculation circuit (10B, 10BB). The odd term calculation circuit calculates odd terms of the modified recurrent equation: a.sub.j =(a.sub.j-2 .times.b.sub.j-1 .times.b.sub.j)+(b.sub.i +c.sub.j-1)+c.sub.j, where j is an odd integer. The even term calculation circuit calculates even terms of the recurrent equations: a.sub.k =(a.sub.k-2 .times.b.sub.k-1 .times.b.sub.k)+(b.sub.k .times.c.sub.k-1)+c.sub.k, where k is an even integer. The data distribution circuit receives an initial, data a.sub.0 and input vector (operand) data (b.sub.i) and (c.sub.

Abstract: A vector access control system for a computer system is provided, including vector registers and a memory access pipeline function unit having an indirect address match checking circuit for detecting a coincidence between data of elements accessed by a plurality of indirect address data. An access to a main storage is carried out by adding a plurality of data, which are read from the vector registers and are necessary for an indirect address access, to a leading address. When a coincidence of data of elements and a resultant conflict between access requests to the main storage is detected by the indirect address match checking circuit, only a predetermined access request in the conflicting access requests is allowed.

Abstract: A vector processing system is provided, including a store data alignment circuit for a pipe line structure and improving an access time for storing vector-processed data in main storage units connected thereto. The vector processing system includes: a unit for storing vector-processed data; a unit for controlling the reading of the vector-processed data from the vector-processed data storing unit, and the storing of the read data in the main storage units; a unit correspondingly provided to the main storage unit, for receiving the vector-processed data through the read and store control unit and buffering the data therein; a unit for managing the data stored in the data buffering unit; and a unit for determining a priority of a store access to the main storage unit. The read and store control unit and the main storage unit are operable in response to the priority determined by the priority determining unit.

Abstract: A vector processing unit in which a plurality of successive vector elements of a vector can be read out from a vector register simultaneously in one machine cycle and a plurality of successive vector elements of a vector can be written into the vector register simultaneously in one machine cycle. The vector processing unit is capable of executing compression transformation and extension transformation of a vector efficiently with simplified hardware.