Abstract: In a communication control apparatus comprising a receiving section which receives reception cells supplied from a network via a physical layer device and which includes a memory for selectively storing the reception cells as stored cells, the receiving section comprises an address filtering section for identifying a value of a particular address included in a payload field of a first cell for a reception packet to produce an address filtered signal indicative of an identified value. A write-in control section determines whether or not the reception packet should be received on the basis of the identified value indicated by the address filtered signal. The write-in control section writes the reception packet in the memory when the reception packet should be received. The write-in control section discards the reception packet without writing it in the memory when the reception packet should be not received.

Abstract: In an ATM reception packet timeout detecting method, a timeout of an ATM reception packet is detected by using a CAM on the reception side of an ATM communication controller. An ATM reception packet timeout detecting apparatus includes a CAM, a write/search mode switching section, a timer section, and an adder. The CAM is made up of a selector for switching input data in accordance with a write/search mode, a cell array in which a timeout detection time is registered, an address decoder for decoding the write/read address of contents of the cell array from a reception VC, and a priority encoder for outputting a coincidence signal and a coincidence address on the basis of outputs from the cell array. The timer section has a counter that is incremented in synchronism with a system clock supplied from a system bus side. The adder adds the timeout allowable time for each VC to the counter value of the timer section.

Abstract: In an ATM communication control device, a cell transmission timing via a virtual channel is determined based on peak rate instructed in a received predetermined ATM cell, such as a received RM cell. Upon determining the transmission timing, a next transmission time for a virtual channel is stored in a CAM, and when a counter value agrees with the stored transmission time, the virtual channel corresponding to an address storing the agreed transmission time is determined as a virtual channel for transmission. The CAM may be replaced by a combination of comparators and a normal storage device.

Abstract: A frame synchronization circuit which detects a frame synchronization bit allotted in a particular position within a receiving data string includes a shift register, a synchronization pattern detection circuit and a control circuit. The shift register receives and stores the receiving data string and outputs a parallel data string. The synchronization pattern detection circuit receives the parallel data string outputted from the shift register in synchronization with a clock signal and makes decisions simultaneously on the matching/non-matching of a parallel data string of totally r bits disposed in an n bit cycle within the receiving data string with r kinds of predetermined synchronization patterns of r bits. The control circuit receives an output of the synchronization pattern detection circuit, and outputs either a signal indicative of the in-synchronization state through a terminal or a signal indicative of the out-of-synchronization state through a terminal.