Abstract: An information sharing support system is provided. The system includes a first information processing device connected to a projector device for projecting an image on a projection area, and to an image pick-up device for picking up an image of the projection area; an inputting unit that inputs an event in a first layer, inputs a second annotation image as a part of a first annotation image associated with the event to a second layer, inputs a third annotation image as the remaining part of the first annotation image to a third layer, and inputs a document to a fourth layer; a transmitting unit that transmits the second annotation image; and a second information processing device that allocates the picked-up image to the second layer, and includes a display that displays the third annotation image and the document in an overlapping fashion.

Abstract: A temperature sensing circuit activates a sensing signal when sensing that a temperature inside a semiconductor integrated circuit is lower than a predetermined temperature. A heat generation control circuit activates a heat generation control signal when the sensing signal is activated. When the heat generation control signal is activated, a current is generated inside a memory circuit to raise the temperature inside the semiconductor integrated circuit.

Abstract: In a semiconductor integrated circuit including a memory macro, such as a DRAM, an SRAM, a ROM, a flash memory, or the like, and a logic circuit, memory macro test-dedicated pads are provided on the memory macro, whereby an increase in the number of normal pads is reduced or prevented to reduce or prevent an increase in the chip area. Moreover, by fixing arrangement (positions) of the pads provided on the memory macro between memory macros of a plurality of memory macro-including semiconductor integrated circuits, a single common probe card for a single chip can be used for the memory macro-including semiconductor integrated circuits, thereby providing low-cost testing.

Abstract: An information processing system includes an acceptance section, a first processing section, a conversion section and a second processing section. The acceptance section accepts first storage location information that is indicative of where a first electronic file in a first storage unit is stored. The first processing section processes the first electronic file in accordance with a first processing content. The conversion section converts the first storage location information to second storage location information that is indicative of where a second electronic file in a second storage unit is stored. The second electronic file has an identical content as that of the first electronic file. The second processing section processes the second electronic file in accordance with a second processing content.

Abstract: Provided is a photographing apparatus that includes a photographing section that photographs a subject, and a controller that controls a photographing range of the photographing section based on a range specification image that is projected onto the subject.

Abstract: An information processing system includes first to third information processing apparatuses and a communication control apparatus that controls communications among the first to third information processing apparatuses. The communication control apparatus includes: an acquisition unit that acquires information concerning a communication quality between the first and second information processing apparatuses; a setting unit that sets communications between the first and third information processing apparatus based on the information concerning the communication quality acquired by the acquisition unit; and a transfer unit that transfers information transmitted from the first information processing apparatus to the second information processing apparatus, to the third information processing apparatus as well as the second information processing apparatus.

Abstract: An information sharing support system includes: a first information processing device connected to a projector device for projecting an image on a projection area including an object therein, and to an image pick-up device for picking up an image of the projection area including the object; an inputting unit that inputs an event in a first layer, inputs a second annotation image as a part of a first annotation image associated with the event to a second layer, inputs a third annotation image as the remaining part of the first annotation image to a third layer, and inputs a document to a fourth layer; a transmitting unit that transmits the second annotation image to the projector device; a receiving unit that receives a picked-up image from the image pick-up device; and a second information processing device that allocates the picked-up image to the second layer, and includes a display that displays the third annotation image and the document in an overlapping fashion.

Abstract: An information processing method using a terminal apparatus, including: applying light with a concentric ring-like interference fringe pattern on one of subjects by using a pointer provided in the terminal apparatus; detecting the interference fringe pattern by using a detector; calculating an optical axis of the pointer on the basis of a detection signal obtained from the detector; specifying attribute information of the subject on the basis of arrangement information of the subject intersected by the optical axis in the condition that arrangement information of the subjects and attribute information of the subjects are stored in a storage device in advance while the arrangement information of each subject and the attribute information of the subject are associated with each other; and displaying the attribute information of the specified subject on the terminal apparatus.

Abstract: Conventionally, when a burn-in test is performed by means of utilizing a memory BIST circuit, a control of a reset operation for the memory BIST circuit is required from an external source. According to the present invention, it is configured that the memory BIST circuit is used for the burn-in test of a memory macro, and a BIST reset control circuit detects a memory BIST test completion signal from the memory BIST circuit, and automatically resets the memory BIST circuit. Thereby, repetitive continuous tests to the memory macro by the memory BIST circuit can be achieved, and the burn-in test by means of utilizing the memory BIST circuit can be performed.

Abstract: An information processing method using a terminal apparatus, including: applying light with a concentric ring-like interference fringe pattern on one of subjects by using a pointer provided in the terminal apparatus; detecting the interference fringe pattern by using a detector; calculating an optical axis of the pointer on the basis of a detection signal obtained from the detector; specifying attribute information of the subject on the basis of arrangement information of the subject intersected by the optical axis in the condition that arrangement information of the subjects and attribute information of the subjects are stored in a storage device in advance while the arrangement information of each subject and the attribute information of the subject are associated with each other; and displaying the attribute information of the specified subject on the terminal apparatus.

Abstract: Conventionally, when a burn-in test is performed by means of utilizing a memory BIST circuit, a control of a reset operation for the memory BIST circuit is required from an external source. According to the present invention, it is configured that the memory BIST circuit is used for the burn-in test of a memory macro, and a BIST reset control circuit detects a memory BIST test completion signal from the memory BIST circuit, and automatically resets the memory BIST circuit. Thereby, repetitive continuous tests to the memory macro by the memory BIST circuit can be achieved, and the burn-in test by means of utilizing the memory BIST circuit can be performed.

Abstract: In a conventional DRAM, row addresses and column addresses are latched by DFF and decoding of addresses is started a certain time after a clock rise, and it takes a long time after the clock rise until the decoding is completed, having a problem that it is not possible to perform read/write at high speed. The present invention adopts a configuration connecting latch circuits such as the row address latch circuits and column address latch circuits using a scan chain. This makes decoding of row addresses and column addresses start when the clock is “L”, making it possible to complete decoding on the rise of each operation clock cycle, shorten the operation clock cycle and speed up read/write. The conventional art conducts a test on the connection between the row addresses and column addresses of the logic section and memory through an actual operation test of the entire LSI, resulting in a low circuit failure detection rate.

Abstract: In a conventional DRAM, row addresses and column addresses are latched by DFF and decoding of addresses is started a certain time after a clock rise, and it takes a long time after the clock rise until the decoding is completed, having a problem that it is not possible to perform read/write at high speed. The present invention adopts a configuration connecting latch circuits such as the row address latch circuits and column address latch circuits using a scan chain. This makes decoding of row addresses and column addresses start when the clock is “L”, making it possible to complete decoding on the rise of each operation clock cycle, shorten the operation clock cycle and speed up read/write. The conventional art conducts a test on the connection between the row addresses and column addresses of the logic section and memory through an actual operation test of the entire LSI, resulting in a low circuit failure detection rate.

Abstract: In a conventional DRAM, row addresses and column addresses are latched by DFF and decoding of addresses is started a certain time after a clock rise, and it takes a long time after the clock rise until the decoding is completed, having a problem that it is not possible to perform read/write at high speed. The present invention adopts a configuration connecting latch circuits such as the row address latch circuits and column address latch circuits using a scan chain. This makes decoding of row addresses and column addresses start when the clock is “L”, making it possible to complete decoding on the rise of each operation clock cycle, shorten the operation clock cycle and speed up read/write. The conventional art conducts a test on the connection between the row addresses and column addresses of the logic section and memory through an actual operation test of the entire LSI, resulting in a low circuit failure detection rate.

Abstract: In a conventional DRAM, row addresses and column addresses are latched by DFF and decoding of addresses is started a certain time after a clock rise, and it takes a long time after the clock rise until the decoding is completed, having a problem that it is not possible to perform read/write at high speed. The present invention adopts a configuration connecting latch circuits such as the row address latch circuits and column address latch circuits using a scan chain. This makes decoding of row addresses and column addresses start when the clock is “L”, making it possible to complete decoding on the rise of each operation clock cycle, shorten the operation clock cycle and speed up read/write. The conventional art conducts a test on the connection between the row addresses and column addresses of the logic section and memory through an actual operation test of the entire LSI, resulting in a low circuit failure detection rate.

Abstract: A high-speed image forming apparatus may alleviate a load imposed upon the drawing processing of the gradation. A drawing unit writes data in a page buffer while executing the drawing processing by using the drawing data stored in a drawing data storage unit. At that time, when generation of the gradation is instructed, the drawing unit accesses a gradation generation unit. The gradation generation unit sets a plurality of adjacent band-like regions which are perpendicular to a straight line connecting a start point with an end point and in which color values therein become uniform by using the vector of the changing direction of the transferred color and the color information at the start and endpoints, obtains the intersection point between the boundary of the band-like region and the scanning line, and sets such intersection point as the color changing point.

Abstract: For enabling the self-test of a memory with a small number of input and output pins, and the burn-in tests of a memory and a logic to be carried out simultaneously in a memory/logic circuit mixed system LSI, a test data, an address and a memory control signal required for the test of the memory are generated using the divided-frequency output signal of an address generator, i.e., frequency-divider of an external clock, and a mixer circuit for periodically inverting a pass/fail signal as the test result is provided. This enables the test of the memory with a total of 2 pins of input and output in all. Thus, it becomes possible to test the memory and the logic circuit simultaneously at the time of burn-in test thereof.

Abstract: In an image forming apparatus which forms an image by parallel-processing an instruction set described in a page description language and in which image data can be efficiently processed by properly dividing the sequence of instructions for parallel-processing, interpreting means generates an intermediate representation independent of a language by interpreting an image plotting instruction described in a page description language according to a grammar of a page description language. The intermediate representation is divided into blocks according to a particle size designated by particle size designating means. Divided blocks are distributed by distributing means to converting means which can operate in parallel to each other and thereby converted into pixel representations. Partial converted pixel representations are synthesized by synthesizing means into a page image.

Abstract: A process for producing 2,2'-bis(hydroxymethyl)alkanoic acid of the present invention, comprises:a 2,2'-bis(hydroxymethyl)alkanal production step (A1) of reacting aliphatic aldehyde having two hydrogen atoms bonded to .alpha.

Abstract: When an instruction sequence is divided into a plurality of subsequences and executed by a plurality of painting instruction operators, an effective parallel schedule can be drawn up even if there may exist image elements overlapped one another, thus enabling high-speed painting instruction to be executed. There are provided a control information configuror for giving a directed branch to a subsequence having order dependence upon receipt of subsequences divided by a sequence divider and for excluding, when the subsequence with the branch given has another subsequence having order dependence, the subsequence from the determination targets for order dependence; and a scheduler for processing, when on allocating subsequences to a painting instruction operator at the execution target, the subsequences to be allocated are dependent upon subsequences to be executed outside of the allocatee, after the processing of subsequences at the host is awaited.