Patents by Inventor Shoji Sawamura
Shoji Sawamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11868285Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.Type: GrantFiled: November 18, 2022Date of Patent: January 9, 2024Assignee: Kioxia CorporationInventors: Toshio Fujisawa, Nobuhiro Kondo, Shoji Sawamura, Kenichi Maeda, Atsushi Kunimatsu
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Publication number: 20230078983Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.Type: ApplicationFiled: November 18, 2022Publication date: March 16, 2023Inventors: Toshio Fujisawa, Nobuhiro Kondo, Shoji Sawamura, Kenichi Maeda, Atsushi Kunimatsu
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Patent number: 11537536Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.Type: GrantFiled: January 22, 2021Date of Patent: December 27, 2022Assignee: Kioxia CorporationInventors: Toshio Fujisawa, Nobuhiro Kondo, Shoji Sawamura, Kenichi Maeda, Atsushi Kunimatsu
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Publication number: 20210141746Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.Type: ApplicationFiled: January 22, 2021Publication date: May 13, 2021Inventors: Toshio Fujisawa, Nobuhiro Kondo, Shoji Sawamura, Kenichi Maeda, Atsushi Kunimatsu
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Patent number: 10929315Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.Type: GrantFiled: June 29, 2018Date of Patent: February 23, 2021Assignee: Toshiba Memory CorporationInventors: Toshio Fujisawa, Nobuhiro Kondo, Shoji Sawamura, Kenichi Maeda, Atsushi Kunimatsu
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Patent number: 10459846Abstract: According to one embodiment, a memory system is connectable to a host device including a first memory. The memory system includes a memory controller and a second memory in which data from a host device is stored. The memory controller includes a third memory, a first unit and a second unit and has a first space. The first unit designates a first address in the first space. The second unit converts, by using a conversion table, the first address into a second address in a first area of the first memory. The conversion table includes a plurality of layers and includes a first conversion table of a top layer and a second conversion table of a layer lower than the first conversion table. The first conversion table is stored in the third memory. The second conversion table is stored in a second area of the first memory.Type: GrantFiled: March 9, 2016Date of Patent: October 29, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yukimasa Miyamoto, Toru Katagiri, Shoji Sawamura
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Publication number: 20180307632Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.Type: ApplicationFiled: June 29, 2018Publication date: October 25, 2018Inventors: Toshio Fujisawa, Nobuhiro Kondo, Shoji Sawamura, Kenichi Maeda, Atsushi Kunimatsu
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Patent number: 10042786Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.Type: GrantFiled: July 24, 2015Date of Patent: August 7, 2018Assignee: Toshiba Memory CorporationInventors: Toshio Fujisawa, Nobuhiro Kondo, Shoji Sawamura, Kenichi Maeda, Atsushi Kunimatsu
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Patent number: 9864548Abstract: According to one embodiment, a memory module includes a volatile memory, a nonvolatile memory, and a controller. The volatile memory is data readable and writable. The nonvolatile memory is data readable and writable and stores therein correspondence information containing an attribute indicating any of volatile, nonvolatile, and both of volatile and nonvolatile associated with an address in an address space assigned to the volatile memory and the nonvolatile memory. The controller reads data from and writes data to the volatile memory or the nonvolatile memory, referring to the correspondence information.Type: GrantFiled: March 4, 2016Date of Patent: January 9, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shoji Sawamura, Nobuhiro Kondo, Kenichi Maeda, Kenichiro Yoshii
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Publication number: 20170075815Abstract: According to one embodiment, a memory system is connectable to a host device including a first memory. The memory system includes a memory controller and a second memory in which data from a host device is stored. The memory controller includes a third memory, a first unit and a second unit and has a first space. The first unit designates a first address in the first space. The second unit converts, by using a conversion table, the first address into a second address in a first area of the first memory. The conversion table includes a plurality of layers and includes a first conversion table of a top layer and a second conversion table of a layer lower than the first conversion table. The first conversion table is stored in the third memory. The second conversion table is stored in a second area of the first memory.Type: ApplicationFiled: March 9, 2016Publication date: March 16, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yukimasa MIYAMOTO, Toru KATAGIRI, Shoji SAWAMURA
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Publication number: 20170075630Abstract: According to one embodiment, a memory module includes a volatile memory, a nonvolatile memory, and a controller. The volatile memory is data readable and writable. The nonvolatile memory is data readable and writable and stores therein correspondence information containing an attribute indicating any of volatile, nonvolatile, and both of volatile and nonvolatile associated with an address in an address space assigned to the volatile memory and the nonvolatile memory. The controller reads data from and writes data to the volatile memory or the nonvolatile memory, referring to the correspondence information.Type: ApplicationFiled: March 4, 2016Publication date: March 16, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Shoji SAWAMURA, Nobuhiro Kondo, Kenichi Maeda, Kenichiro Yoshii
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Patent number: 9575887Abstract: A memory device according to an embodiment includes a non-volatile storage device, a volatile storage device that stores saved data which is saved in the host-side storage device when a first operation mode changing process is executed by the memory device, and a control unit. The control unit transmits, to the host device, a write command that is an instruction to write the saved data to the host-side storage device and the saved data, when the first operation mode changing process is executed by the memory device.Type: GrantFiled: February 3, 2014Date of Patent: February 21, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Shoji Sawamura, Nobuhiro Kondo, Takaya Horiki, Daisuke Iwai
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Publication number: 20160267027Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.Type: ApplicationFiled: July 24, 2015Publication date: September 15, 2016Inventors: Toshio Fujisawa, Nobuhiro Kondo, Shoji Sawamura, Kenichi Maeda, Atsushi Kunimatsu
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Patent number: 9354818Abstract: According to one embodiment, a data storing method includes saving data stored in a memory device to a host device and verifying validity or accuracy of the data saved in the host device.Type: GrantFiled: September 3, 2014Date of Patent: May 31, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Yaotung Kuo, Koichi Nagai, Shoji Sawamura, Nobuhiro Kondo
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Publication number: 20150242141Abstract: According to one embodiment, a data storing method includes saving data stored in a memory device to a host device and verifying validity or accuracy of the data saved in the host device.Type: ApplicationFiled: September 3, 2014Publication date: August 27, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Yaotung KUO, Koichi Nagai, Shoji Sawamura, Nobuhiro Kondo
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Publication number: 20150074330Abstract: A memory device according to an embodiment includes a non-volatile storage device, a volatile storage device that stores saved data which is saved in the host-side storage device when a first operation mode changing process is executed by the memory device, and a control unit. The control unit transmits, to the host device, a write command that is an instruction to write the saved data to the host-side storage device and the saved data, when the first operation mode changing process is executed by the memory device.Type: ApplicationFiled: February 3, 2014Publication date: March 12, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Shoji SAWAMURA, Nobuhiro Kondo, Takaya Horiki, Daisuke Iwai
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Publication number: 20150058532Abstract: A memory device of an embodiment includes a non-volatile storage device, and a volatile storage device that stores observation information indicating a state of the memory device. The memory device is provided with a controller that executes an observation information sending process that sends a write command, which is an instruction to write the observation information in the host-side storage device, and the observation information to the host device. Further, the controller repeats the observation information sending process plural times in response to one sending request from the host device.Type: ApplicationFiled: November 21, 2013Publication date: February 26, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Shigenori SUGIMOTO, Shoji SAWAMURA, Takaya HORIKI, Daisuke IWAI
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Patent number: 7627771Abstract: A clock control hierarchy is provided that is comprised of synchronous and asynchronous hold request signals that are used to start and stop functional units of a chip. Pervasive logic is provided that uses a synchronous “chip hold” signal and asynchronous latch/functional unit hold signals to individually target functional units and latches that are to remain in a held state once the “chip hold” state is released. With the present invention, a chip hold request is first activated followed by scannable latch and non-scannable latch hold requests being activated to identify which latches will be clocked or not clocked when the chip hold is released. Functional unit hold signals are activated to place certain ones of the functional units of the chip in a hold state. The chip hold request is deactivated and the chip operates with the selected functional units and latches being maintained in a held state.Type: GrantFiled: October 4, 2005Date of Patent: December 1, 2009Assignee: International Business Machines CorporationInventors: Nathan P. Chelstrom, Mack W. Riley, Shoji Sawamura
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Publication number: 20090222251Abstract: A design structure for a integrated circuit interfacing system may be embodied in a machine readable medium for designing, manufacturing or testing a integrated circuit. In one embodiment, the design structure specifies an integrated circuit that includes multiple interfaces. The design structure may specify that each of the interfaces couples to a respective set of registers or storage elements on the integrated circuit. The design structure may also specify a bridge circuit on the integrated circuit that switchably couples the two interfaces together such that one interface may communicate with the registers that associate with that interface as well as the registers that associate with the other interface.Type: ApplicationFiled: December 31, 2008Publication date: September 3, 2009Applicant: International Business Machines CorporationInventors: Tilman Gloekler, Ingemar Holm, Ralph C. Koester, Mack Wayne Riley, Shoji Sawamura, Iwao Takiguchi
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Publication number: 20080147901Abstract: In one embodiment, the disclosed methodology and apparatus involves an integrated circuit that includes multiple interfaces. Each of the interfaces couples to a respective set of registers or storage elements on the integrated circuit. A bridge circuit on the integrated circuit switchably couples the two interfaces together such that one interface may communicate with the registers that associate with that interface as well as the registers that associate with the other interface.Type: ApplicationFiled: October 31, 2006Publication date: June 19, 2008Applicant: IBM CorporationInventors: Tilman Gloekler, Ingemar Holm, Ralph C. Koester, Mack Wayne Riley, Shoji Sawamura, Iwao Takiguchi